Patents by Inventor Hui Nie

Hui Nie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250089370
    Abstract: The present disclosure provides a display panel, including a display area and a bezel area surrounding the display area, edge lines of the display area and the bezel area are arc edge lines and matched with each other in shape, the display panel includes a peripheral circuit and peripheral signal lines, which are distributed in the bezel area, and further includes an array substrate and a color filter substrate which are not overlapped at edges thereof on a first side, and in a portion of the bezel area where the edges on the first side are not located, a distance between the peripheral signal line, closest to an outer edge of the bezel area, and the outer edge of the bezel area is in a range of 0.35±0.2 micrometers, the outer edge of the bezel area is an edge of the bezel area away from the display area.
    Type: Application
    Filed: December 26, 2022
    Publication date: March 13, 2025
    Inventors: Desheng WANG, Zhichao YANG, Yong ZHANG, Jian WANG, Qi DENG, Lingfang NIE, Longhu HAO, Zanwu GUO, Hui LI
  • Patent number: 12242286
    Abstract: Provided are a method, system and device for global path planning for an unmanned vehicle in an off-road environment. The method includes: obtaining satellite elevation data and a satellite remote sensing image of a current off-road environment; constructing a digital elevation model (DEM); determining slope and land surface relief of each grid in the current off-road environment; performing gray processing on the satellite remote sensing image to obtain grayscale values of the grids; determining traversal costs of the grids corresponding to different ground types; constructing a global grid map based on the slope and the land surface relief of each grid, as well as the traversal costs corresponding to the different ground types; determining a rugged terrain potential field and path costs; and searching for paths using a Bresenham's line algorithm and Theta* algorithm based on the rugged terrain potential field and the path costs, to generate a global path.
    Type: Grant
    Filed: August 19, 2024
    Date of Patent: March 4, 2025
    Assignee: Beijing Institute of Technology
    Inventors: Shida Nie, Yujia Xie, Zhihao Liao, Hui Liu, Lijin Han, Congshuai Guo
  • Publication number: 20250051355
    Abstract: The present disclosure provides compounds for modulating calcitonin receptor and/or amylin receptor activity, as well as pharmaceutical compositions comprising the compounds disclosed herein. Also provided are methods for treating a calcitonin receptor and/or amylin receptor associated disease or disorder.
    Type: Application
    Filed: August 6, 2024
    Publication date: February 13, 2025
    Inventors: Hui LEI, Cui LI, Chunliang LU, Ding XUE, Haizhen ZHANG, Zhuming ZHANG, Evelyne HOUANG, Jian LIU, Zhe NIE, Anatoly RUVINSKY, Eric THERRIEN
  • Publication number: 20240350448
    Abstract: Described herein is a dichloroacetic acid conjugating diphenyl ethane compound, and a preparation method and an application thereof. The dichloroacetic acid conjugating diphenyl ethane compound has a stable structure, low toxicity, a simple preparation process and a high yield, without necessity to preserve it in a dark place, and has anti-tumor activity against a variety of tumor cells cultured in vitro, and the anti-tumor effect in vivo.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Fanhong WU, Jinwen HUANG, Kangyan XUE, Hui NIE, Fuli LIU, Hui TANG
  • Patent number: 11695088
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: July 4, 2023
    Assignee: Utica Leaseco, LLC
    Inventors: Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
  • Patent number: 11641207
    Abstract: Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: May 2, 2023
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Zhiwei Xu, Jiangbo Chen, Jiabing Liu, Hui Nie, Zhihao Lv, Chunyi Song
  • Patent number: 11463096
    Abstract: Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 4, 2022
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Zhiwei Xu, Jiangbo Chen, Jiabing Liu, Hui Nie, Kaijie Ding, Chunyi Song
  • Publication number: 20220311444
    Abstract: Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started. (FIG.
    Type: Application
    Filed: February 10, 2022
    Publication date: September 29, 2022
    Inventors: Zhiwei XU, Jiangbo CHEN, Jiabing LIU, Hui NIE, Zhihao LV, Chunyi SONG
  • Publication number: 20220077333
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: Hui NIE, Brendan M. KAYES, Isik C. KIZILYALLI
  • Publication number: 20220021394
    Abstract: Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventors: Zhiwei XU, Jiangbo CHEN, Jiabing LIU, Hui NIE, Kaijie DING, Chunyi SONG
  • Patent number: 11211506
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: December 28, 2021
    Assignee: UTICA LEASECO, LLC
    Inventors: Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
  • Patent number: 11121272
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide and an emitter layer. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect. The absorber or base layer has a grading in doping concentration from a first doping level closest to the emitter layer to a second doping level away from the emitter layer, the second doping level being greater than the first doping level.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 14, 2021
    Assignee: UTICA LEASECO, LLC
    Inventors: Andrew J. Ritenour, Brendan M. Kayes, Hui Nie, Isik Kizilyalli
  • Publication number: 20210115330
    Abstract: Method for manufacturing fluoro(hydro)carbon-substituted silicon or germanium quantum dots which comprises the steps of:—reacting a Zintl salt or intermetallic compound of post-transition metals or metalloids of silicon or germanium with a halogen-containing oxidizing agent to form halide-terminated silicon or germanium quantum dots,—reacting the halide-terminated silicon or germanium quantum dots with a fluoro(hydro)carbon agent selected from the group of metal-fluoro (hydro)carbon compounds of the formula MRq, wherein M is a metal selected from Group 1, 2, 4, 11, 12, 13, or 14 of the periodic table of elements, q is an integer which corresponds to the valence of the metal, and R is CFnHm-fluoro/hydro-carbon, wherein n is 1 or 2, m is 0 or 1, and the total of n and m is 2, wherein each R may be the same or different, metal-fluoro (hydro)carbon halide compounds of the formula NQaRp wherein N is a metal selected from Group 1, 2, 4, 11, 12, 13, or 14 of the periodic table of elements, Q is a halogen selected fr
    Type: Application
    Filed: May 1, 2019
    Publication date: April 22, 2021
    Applicants: UNIVERSITEIT TWENTE, UNIVERSITEIT VAN AMSTERDAM
    Inventors: Hui NIE, Katerina NEWELL, Jos Marie Johannes PAULUSSE
  • Patent number: 10916676
    Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 9, 2021
    Assignee: ALTA DEVICES, INC.
    Inventors: Brendan M. Kayes, Hui Nie, Isik C. Kizilyalli
  • Publication number: 20190181281
    Abstract: Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide and an emitter layer. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect. The absorber or base layer has a grading in doping concentration from a first doping level closest to the emitter layer to a second doping level away from the emitter layer, the second doping level being greater than the first doping level.
    Type: Application
    Filed: February 15, 2019
    Publication date: June 13, 2019
    Inventors: Andrew J. RITENOUR, Brendan M. KAYES, Hui NIE, Isik KIZILYALLI
  • Patent number: 10319829
    Abstract: A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 11, 2019
    Assignee: NEXGEN POWER SYSTEMS, INC.
    Inventors: David P. Bour, Thomas R. Prunty, Hui Nie, Madhan M. Raj
  • Publication number: 20180240928
    Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Brendan M. KAYES, Hui NIE, Isik C. KIZILYALLI
  • Publication number: 20180190789
    Abstract: A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.
    Type: Application
    Filed: August 21, 2017
    Publication date: July 5, 2018
    Applicant: NEXGEN POWER SYSTEMS, INC.
    Inventors: David P. Bour, Thomas R. Prunty, Hui Nie, Madhan M. Raj
  • Patent number: 9954131
    Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: April 24, 2018
    Assignee: ALTA DEVICES, INC.
    Inventors: Brendan M. Kayes, Hui Nie, Isik C. Kizilyalli
  • Patent number: D1054025
    Type: Grant
    Filed: August 21, 2024
    Date of Patent: December 10, 2024
    Inventor: Hui Nie