Abstract: A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location.

Abstract: A method and apparatus for managing a communication system including multiple links is presented. A receiver including a First-In, First-out (FIFO) memory receives information communicated on the links. A FIFO is associated with each communication link. Information is written into the FIFO based on a transmitter clock. Information is read out of the FIFO using a receiver clock. The FIFO is used to deskew data communicated across the communication links and re-synchronize the data between the transmitter clock and the receiver clock. A state machine controls the information read out of the FIFO. The state machine includes a deskew enabled state, a deskew disabled state and a reset state. Using the FIFO, the system is able to self reset and transition between the deskew enabled state and the deskew disabled state.

Abstract: A method and apparatus for managing a communication system including multiple links is presented. A receiver including a First-In, First-out (FIFO) memory receives information communicated on the links. A FIFO is associated with each communication link. Information is written into the FIFO based on a transmitter clock. Information is read out of the FIFO using a receiver clock. The FIFO is used to deskew data communicated across the communication links and re-synchronize the data between the transmitter clock and the receiver clock. A state machine controls the information read out of the FIFO. The state machine includes a deskew enabled state, a deskew disabled state and a reset state. Using the FIFO, the system is able to self reset and transition between the deskew enabled state and the deskew disabled state.

Abstract: A data synchronization cell is provided that comprises first and second synchronizers that are generally adjacent one another and that have their M1/S1 clock ports tied together. The result is that both synchronizers are driven by the same clock signal, which arrives substantially simultaneously at the M1/S1 clock ports of the synchronizers due to the fact that the synchronizers are side-by-side and their respective M1/S1 clock lines are tied together. Because the first and second synchronizers of the present invention are adjacent one another and have their respective M1/S1 clock lines tied together, clock skew is negligible and thus no buffer is needed between the synchronizers, which increases the amount of time allowed for resolution, reduces or eliminates the possibility of hold time violations occurring, and reduces the amount of area required to instantiate the synchronization cell.

Abstract: A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location.

Abstract: A data synchronization cell is provided that comprises first and second synchronizers that are generally adjacent one another and that have their M1/S1 clock ports tied together. The result is that both synchronizers are driven by the same clock signal, which arrives substantially simultaneously at the M1/S1 clock ports of the synchronizers due to the fact that the synchronizers are side-by-side and their respective M1/S1 clock lines are tied together. In known synchronization cells, a buffer is placed between the data output port of the first synchronizer and the data input port of the second synchronizer to solve clock skew problems that can cause hold time violations. In such systems, the synchronizers are back-to-back and can have great distances between them and/or receive their clock signals from different trunks. All of these factors decrease the amount of time allowed for resolution and increase the amount of area required to instantiate synchronization cells.