Abstract: The present disclosure relates to a method for forming an integrated chip. The method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. The method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. The method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.

Abstract: Height adjustable seat posts for bicycles are described herein. An example height adjustable seat post includes an upper tube and a lower tube configured in a telescopic arrangement. The height adjustable seat post also includes a shaft coupled to the lower tube and extending into the upper tube a piston assembly coupled to the shaft and disposed in the upper tube. The piston assembly includes a piston dividing the upper tube into a first chamber and a second chamber. The first and second chambers are filled with fluid. The piston assembly includes a valve operable between a closed state in which the fluid is blocked from flowing between the first and second chambers and an open state to enable the fluid to flow between the first and second chambers. The height adjustable seat post also includes a solenoid to control the valve.

Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers are extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degrees. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers is extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degree. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

Abstract: Systems and methods of predicting the retention rates of students attending an educational institution are provided. The method includes receiving an initial dataset related to a cohort of students attending the educational institution, dividing the initial dataset into a training dataset and a testing dataset, training a predictive algorithm via the training dataset to generate a prediction model, and processing the testing dataset via the prediction model to output a prediction results dataset. The prediction results dataset includes a listing of the cohort of students organized from most likely to leave the educational institution to least likely to leave the educational institution. The method includes filtering a percentage of the prediction results dataset to identify a watchlist of students likely to leave the educational institution.

Abstract: The present application relates to antibodies specifically binding to the V-domain immunoglobulin-containing suppressor of T-cell activation (VISTA) at acidic pH and their use in cancer treatment. In some embodiments, the antibodies bind specifically to human VISTA at acidic pH, but do not significantly bind to human VISTA at neutral or physiological pH.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Abstract: Proposed is a method for displaying summary information about a chat message by a user terminal. The method may include receiving information about a chat room comprising at least one chat message from a server, and requesting the server to summarize a summary target message, which is at least a part of the at least one chat message. The method may also include receiving and displaying summary information about the summary target message from the server.

Abstract: Remote sensing satellite data services are limited by lack of data processing and analytic capabilities as current solutions rely on manual interventions, which are inefficient, cost prohibitive for large-scale processing, and prone to human errors. A system that utilizes a large language model to understand user intent and provokes corresponding computer vision models fine-tuned with remote sensing imagery datasets, such as open vocabulary object detection and segmentation model with state-of-the-art model architecture, is provided to enable users to extract useful insights by natural language text query.

Abstract: A computer-implemented method for downscaling an ocean surface wind (OSW). The method comprises: obtaining an input image with a set of wind data, constructing an OSW downscaling model based on a TransUNet architecture; using the OSW downscaling model to generate an output image with a set of resulting wind data according to the input image, and before the OSW downscaling model is used to generate the output image, training the OSW downscaling model according to a plurality of sets of training samples, wherein the OSW downscaling model is trained by optimizing model parameters of the OSW downscaling model in a sense of minimizing a loss function for improving resolution.

Abstract: Height adjustable seat posts for bicycles are described herein. An example height adjustable seat post includes an upper tube and a lower tube configured in a telescopic arrangement. The height adjustable seat post also includes a shaft coupled to the lower tube and extending into the upper tube a piston assembly coupled to the shaft and disposed in the upper tube. The piston assembly includes a piston dividing the upper tube into a first chamber and a second chamber. The first and second chambers are filled with fluid. The piston assembly includes a valve operable between a closed state in which the fluid is blocked from flowing between the first and second chambers and an open state to enable the fluid to flow between the first and second chambers. The height adjustable seat post also includes a solenoid to control the valve.

Abstract: A computer-implemented method for adaptively discretizing a position of a textual object in a document includes receiving, by a computer system, an image of the document and determining, by the computer system, an absolute position of the textual object in the image of the document. The method further includes normalizing, by the computer system, the absolute position to determine a relative position of the textual object. The method also includes calculating, by the computer system, a bin size such that at least one axis of the image is divided into a plurality of separate bins, wherein a distance between each bin along the at least one axis and its adjacent bin equals the bin size. The method includes discretizing, by the computer system, the relative position based on the bin size to determine a discretized position of the textual object; and providing, by the computer system, the discretized position and a textual content of the textual object as an input to a machine learning model.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

Abstract: Systems and methods are described for enhancing performance of a search engine by using pre-existing fine-tuned machine learning models that include domain-specific knowledge. A computing device receives search results from a search engine based on a query, in which the search results include chunk identifiers and a first weight score associated with each chunk identifier. The computing device further determines a subset of search results, which includes a first predetermined number of top-ranked chunk identifiers in the search results. The computing device generates, for each chunk identifier in the subset of search results, one or more second weight scores. Then the computing device generates, via a machine learning model, ensemble scores for the chunk identifiers. Afterwards, the computing device determines a second predetermined number of top-ranked chunk identifiers based on the ensemble scores.

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure includes a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

Abstract: For a coding block of an image, a luma prediction block is generated, a luma residual block is generated, a quantized luma block is generated after transforming the luma residual block using a luma transform type, and the quantized luma block is entropy encoded. A chroma prediction block is generated, a chroma residual block is generated, an initial chroma transform type for the chroma residual block is determined as the luma transform type, a quantized chroma block is generated using the chroma residual block transformed by a final chroma transform type, and the quantized chroma block is entropy encoded. When the initial chroma transform type is other than a default transform type, the final chroma transform type is the initial chroma transform type or the default transform type, and quantized coefficients of the quantized chroma block depend upon quantized coefficients of the quantized luma block.

Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.

Abstract: A method of generating compensating data for a pixel circuit differences in a display device includes displaying a test image of pixels of the display device; generating a first camera image by photographing the test image; applying a test input signal to each of the pixels and sensing corresponding test outputs, wherein the test input signal is at least one of a test current and a test voltage; generating weights for the pixels based on the test outputs; generating a second camera image by applying the weights to the first camera image; and generating compensation data for the pixels based on the second camera image.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.