Patents by Inventor Hui Su

Hui Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254894
    Abstract: A semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.
    Type: Application
    Filed: April 28, 2025
    Publication date: August 7, 2025
    Inventors: Shu-Hui SU, Hsin-Li CHENG, YingKit Felix TSUI
  • Patent number: 12380343
    Abstract: Methods and apparatus for complementary evidence identification in natural language inference. A given question is obtained and a set of N passages is obtained from a database. A probability is determined, for each passage of the set of N passages, of a corresponding passage being a supportive passage for the given question and the set of N passages is ranked based on the determined probabilities. M passages that are ranked 1 to M of the set of N passages are selected. A set of L passages is selected based on a plurality of scores, each score assigned to a set of candidate passages of the set of N passages, each score being based on the determined probabilities, the selected M passages, and a weighted regulation parameter. The set of L passages is provided to a computerized machine learning system to answer the question based on the set of L passages.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 5, 2025
    Assignees: International Business Machines Corporation, Rensselaer Polytechnic Institute
    Inventors: Mo Yu, Li Zhang, Hui Su, Shiyu Chang, Ming Tan, Xiangyang Mou
  • Patent number: 12368282
    Abstract: The present invention proposes an O-band silicon-based high-speed semiconductor laser diode for optical communication and its manufacturing method, by using different buffer layers to form the growth surface of InP material with low dislocation density; N—InAlGaAs is used instead of conventional N—InAlAs electron-blocking layer in the epi-structure to reduce the barrier for electrons to enter the quantum wells from N-type and lower the threshold; a superlattice structure quantum barrier is used instead of a single layer barrier structure to improve the transport of heavy holes in the quantum wells; and the material structure is adjusted to achieve a reliable O-band high direct modulation speed semiconductor laser diode for optical communication on silicon substrate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 22, 2025
    Assignee: FuJian Z.K. Litecore, Ltd.
    Inventors: Zheng Qun Xue, Hui Ying Huang, Chang Ping Zhang, Ze Lei Lin, Rui Yu Fang, Hui Su
  • Patent number: 12365412
    Abstract: A battery compartment, a battery compartment assembly and an electric scooter are provided. The battery compartment is used for an electric scooter, and includes a compartment body and a limiting flange. The electric scooter includes a frame with an opening, and the opening runs through the frame in an up-down direction. The compartment body is configured to penetrate through the opening, and the limiting flange is arranged to an outer side wall of the compartment body and configured to abut against the frame to prevent the compartment body from falling out of the opening downwards.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: July 22, 2025
    Assignee: NINEBOT (CHANGZHOU) TECH CO., LTD.
    Inventors: Zefang Qi, Hui Su
  • Patent number: 12347680
    Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.
    Type: Grant
    Filed: May 20, 2024
    Date of Patent: July 1, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Publication number: 20250206822
    Abstract: The present application relates to antibodies specifically binding to the V-domain immunoglobulin-containing suppressor of T-cell activation (VISTA) at acidic pH and their use in cancer treatment. In some embodiments, the antibodies bind specifically to human VISTA at acidic pH, but do not significantly bind to human VISTA at neutral or physiological pH.
    Type: Application
    Filed: November 25, 2024
    Publication date: June 26, 2025
    Applicants: Five Prime Therapeutics, Inc., Bristol-Myers Squibb Company
    Inventors: Robert J. Johnston, Arvind Rajpal, Paul O. Sheppard, Luis Borges, Andrew Rankin, Keith Sadoon Bahjat, Alan J. Korman, Andy X. Deng, Lin Hui Su, Ginger Rakestraw
  • Publication number: 20250194167
    Abstract: The present disclosure provides a memory device having improved P-N junction and a manufacturing method thereof. The memory device includes a semiconductor substrate having a first surface and defined with an active area under the first surface, a gate structure adjacent to the active area and indented into the semiconductor substrate from the first surface, a doped member extending into the semiconductor substrate and surrounded by the active area, a conductive layer including a first portion extending into the semiconductor substrate from the first surface and a second portion disposed over the doped member and coupled to the first portion, a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active area of the semiconductor substrate, a first contact disposed over the conductive layer, and a conductive pillar disposed over the first contact.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Inventor: KUO-HUI SU
  • Patent number: 12317517
    Abstract: A semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Hsin-Li Cheng, YingKit Felix Tsui
  • Patent number: 12315725
    Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: May 27, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Publication number: 20250149384
    Abstract: The present disclosure relates to a method for forming an integrated chip. The method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. The method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. The method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Inventor: Shu-Hui Su
  • Patent number: 12291297
    Abstract: Height adjustable seat posts for bicycles are described herein. An example height adjustable seat post includes an upper tube and a lower tube configured in a telescopic arrangement. The height adjustable seat post also includes a shaft coupled to the lower tube and extending into the upper tube a piston assembly coupled to the shaft and disposed in the upper tube. The piston assembly includes a piston dividing the upper tube into a first chamber and a second chamber. The first and second chambers are filled with fluid. The piston assembly includes a valve operable between a closed state in which the fluid is blocked from flowing between the first and second chambers and an open state to enable the fluid to flow between the first and second chambers. The height adjustable seat post also includes a solenoid to control the valve.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: May 6, 2025
    Assignee: SRAM, LLC
    Inventors: Rafer Chambers, Christopher Eric Golkiewicz, Chi Hui Su, Donald Frederick Coffman, Alex Kyle McGee, Charles Dunlap
  • Publication number: 20250140672
    Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers is extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degree. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Inventor: KUO-HUI SU
  • Publication number: 20250140675
    Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers are extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degrees. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 1, 2025
    Inventor: KUO-HUI SU
  • Publication number: 20250129166
    Abstract: The present application relates to antibodies specifically binding to the V-domain immunoglobulin-containing suppressor of T-cell activation (VISTA) at acidic pH and their use in cancer treatment. In some embodiments, the antibodies bind specifically to human VISTA at acidic pH, but do not significantly bind to human VISTA at neutral or physiological pH.
    Type: Application
    Filed: November 7, 2024
    Publication date: April 24, 2025
    Applicants: Five Prime Therapeutics, Inc., Bristol-Myers Squibb Company
    Inventors: Robert J. Johnston, Arvind Rajpal, Paul O. Sheppard, Luis Borges, Andrew Rankin, Keith Sadoon Bahjat, Alan J. Korman, Xiaodi Deng, Lin Hui Su, Ginger Rakestraw, Jason R. Pinckney, David A. Critton, Guodong Chen, Richard Y. Huang, Ekaterina G. Deyanova
  • Publication number: 20250131520
    Abstract: Systems and methods of predicting the retention rates of students attending an educational institution are provided. The method includes receiving an initial dataset related to a cohort of students attending the educational institution, dividing the initial dataset into a training dataset and a testing dataset, training a predictive algorithm via the training dataset to generate a prediction model, and processing the testing dataset via the prediction model to output a prediction results dataset. The prediction results dataset includes a listing of the cohort of students organized from most likely to leave the educational institution to least likely to leave the educational institution. The method includes filtering a percentage of the prediction results dataset to identify a watchlist of students likely to leave the educational institution.
    Type: Application
    Filed: February 3, 2023
    Publication date: April 24, 2025
    Applicant: Rensselaer Polytechnic Institute
    Inventors: Jasmine Yang, Lu Enzhe, Jiarun Li, Keith Moo-Young, Yihui Yang, Hui Su, Yifan LIU
  • Publication number: 20250124542
    Abstract: A computer-implemented method for downscaling an ocean surface wind (OSW). The method comprises: obtaining an input image with a set of wind data, constructing an OSW downscaling model based on a TransUNet architecture; using the OSW downscaling model to generate an output image with a set of resulting wind data according to the input image, and before the OSW downscaling model is used to generate the output image, training the OSW downscaling model according to a plurality of sets of training samples, wherein the OSW downscaling model is trained by optimizing model parameters of the OSW downscaling model in a sense of minimizing a loss function for improving resolution.
    Type: Application
    Filed: October 10, 2024
    Publication date: April 17, 2025
    Inventors: Hui SU, Enze ZHANG
  • Publication number: 20250126086
    Abstract: Proposed is a method for displaying summary information about a chat message by a user terminal. The method may include receiving information about a chat room comprising at least one chat message from a server, and requesting the server to summarize a summary target message, which is at least a part of the at least one chat message. The method may also include receiving and displaying summary information about the summary target message from the server.
    Type: Application
    Filed: September 25, 2024
    Publication date: April 17, 2025
    Inventors: Sun Joo OH, Hui Su KIM, Heon Seob SEOK, Min Seok CHAE, Hee June KIM, Dae Seon KIM, Seung Hyun LEE, Bong Gyun KANG, Soo Young BYUN, Yun Gu KANG, Ji Won CHOI
  • Publication number: 20250125191
    Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.
    Type: Application
    Filed: November 24, 2023
    Publication date: April 17, 2025
    Inventor: KUO-HUI SU
  • Publication number: 20250125190
    Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Inventor: KUO-HUI SU
  • Publication number: 20250124078
    Abstract: Remote sensing satellite data services are limited by lack of data processing and analytic capabilities as current solutions rely on manual interventions, which are inefficient, cost prohibitive for large-scale processing, and prone to human errors. A system that utilizes a large language model to understand user intent and provokes corresponding computer vision models fine-tuned with remote sensing imagery datasets, such as open vocabulary object detection and segmentation model with state-of-the-art model architecture, is provided to enable users to extract useful insights by natural language text query.
    Type: Application
    Filed: October 10, 2024
    Publication date: April 17, 2025
    Inventors: Hui SU, Weifan XU