Patents by Inventor Hui-Ting Chou

Hui-Ting Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916126
    Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20220275390
    Abstract: Described herein are chimeric polypeptides that include one or more Rubisco-binding motifs (RBMs) and a heterologous polypeptide. Additional aspects of the present disclosure provide genetically altered plants having a chimeric polypeptide including one or more Rubisco-binding motifs (RBMs) and a heterologous polypeptide. Further aspects of the present disclosure relate to genetically altered plants having a stabilized polypeptide including two or more RBMs and one or both of an algal Rubisco-binding membrane protein (RBMP) and a Rubisco small subunit (SSU) protein. Other aspects of the present disclosure relate to methods of making such chimeric polypeptides and plants, as well as cultivating these genetically altered plants.
    Type: Application
    Filed: July 30, 2020
    Publication date: September 1, 2022
    Applicants: The Trustees of Princeton University, The Board of Trustees of the Leland Stanford Junior University, University of York, Howard Hughes Medical Institute
    Inventors: Martin C. Jonikas, Moritz Meyer, Shan He, Alan Itakura, Vivian Chen Wong, Luke Colin Martin Mackinder, Zhiheng Yu, Doreen Matthies, Hui-Ting Chou