Patents by Inventor Hui-Tzu Lin

Hui-Tzu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5929509
    Abstract: A wafer edge seal ring structure is disclosed to provide reduced particulate contaminant generation during wafer processing of high density integrated circuits. The structure is formed by delimiting the deposition of layers at the peripheral edges of wafers. It is shown that as each layer is deposited and then essentially trimmed back from the edge of the wafer through a judicious use of mask and etching, and/or edge-bead rinsing (EBR) and later sealed by wafer edge exposure (WEE), the otherwise present abnormal growth of layers are prevented from building up into protrusions at the edge of wafer that later peel or break up to form particulate matter and fine dust. The method, which is also disclosed, teaches how each layer is recessed at appropriate distances from the wafer edge and how the whole ring structure is sealed against attacking particles.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: July 27, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Heng Shen, Hui-Tzu Lin
  • Patent number: 5913979
    Abstract: The present invention provides a method for removing unwanted coating layer at wafer edge by first immersing the wafer edge in a cleaning solution and then immersing in a rinsing solution such as deionized water to remove the residual cleaning solution from the surface of the wafer. The wafer can be dried in a subsequent spin dry process.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: June 22, 1999
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chih-Heng Shen, Hui-Tzu Lin
  • Patent number: 5723385
    Abstract: A wafer edge seal ring structure is disclosed to provide reduced particulate contaminant generation during wafer processing of high density integrated circuits. The structure is formed by delimiting the deposition of layers at the peripheral edges of wafers. It is shown that as each layer is deposited and then essentially trimmed back from the edge of the wafer through a judicious use of mask and etching, and/or edge-bead rinsing (EBR) and later sealed by wafer edge exposure (WEE), the otherwise present abnormal growth of layers are prevented from building up into protrusions at the edge of wafer that later peel or break up to form particulate matter and fine dust. The method, which is also disclosed, teaches how each layer is recessed at appropriate distances from the wafer edge and how the whole ring structure is sealed against attacking particles.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: March 3, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Chih-Heng Shen, Hui-Tzu Lin