Patents by Inventor Hui Wei
Hui Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12253078Abstract: Provided are a pressure-pump cartridge and a pressure pump, where the pressure-pump cartridge includes a cylinder, where the cylinder has a first chamber, a piston chamber and a second chamber hat are in communication in sequence, and the piston chamber is used for being in sealing fit with a piston. An end of the first chamber remote from the piston chamber is provided with a first opening allowing entry of the piston, and during installation, the piston enters the first chamber by the first opening and enters the piston chamber after passing through the first chamber, and meanwhile, the first chamber is configured to be in a clearance fit with the piston, such that the size of the first chamber is larger than that of the piston.Type: GrantFiled: June 16, 2022Date of Patent: March 18, 2025Assignee: MICRO-TECH (NANJING) CO., LTD.Inventors: Hongyan Jin, Hui Liu, Jinwei Pang, Derong Leng, Changqing Li, Jiefeng Xi, Ning Li, Chunjun Liu, Zhi Tang, Jianyu Wei
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Patent number: 12252851Abstract: The present invention provides a method of calculating the dosage of phase change coarse aggregate, which comprises the steps of setting a regulatory temperature difference of a thermoregulating cement-stabilized layer, the regulatory temperature difference being the difference between the peak temperature of the thermoregulating cement-stabilized layer and the peak temperature of a conventional cement-stabilized layer, wherein the thermoregulating cement-stabilized layer is mixed with a phase change coarse aggregate, while the conventional cement-stabilized layer is not mixed with a phase change coarse aggregate; calculating a regulatory heat based on the regulatory temperature difference, wherein when a temperature change of the conventional cement-stabilized layer is the regulatory temperature difference, a heat change of the conventional cement-stabilized layer is the regulatory heat; and calculating a volume occupied by the phase change coarse aggregate in the thermoregulating cement-stabilized layer basType: GrantFiled: November 20, 2024Date of Patent: March 18, 2025Assignee: CCCC FIRST HIGHWAY CONSULTANTS CO., LTD.Inventors: Binhua Hu, Long Jin, Yuanhong Dong, Zijun Li, Jianbing Chen, Yan Mu, Hui Peng, Yao Wei, Wansheng Pei, Tian Sun
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Publication number: 20250087627Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.Type: ApplicationFiled: November 26, 2024Publication date: March 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
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Patent number: 12249542Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.Type: GrantFiled: November 17, 2023Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
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Patent number: 12248231Abstract: The present disclosure provides a connecting bracket and a camera system. The camera system may include a first lens unit, a second lens unit, a first image sensor unit corresponding to the first lens unit, a second image sensor unit corresponding to the second lens unit, and a connecting bracket configured to connect the first lens unit and the first image sensor unit to form a first camera component, and connect the second lens unit and the second image sensor unit to form a second camera component. A predetermined angle may be formed between a first optical axis of the first camera component and a second optical axis of the second camera component.Type: GrantFiled: July 27, 2022Date of Patent: March 11, 2025Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.Inventors: Dong Ye, Hui Zhan, Xiyang Wei
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Publication number: 20250073955Abstract: The present disclosure provides an under-wire spray cleaning device for a wire cutting machine including: a spray assembly connected to a trough body, wherein the trough body is entirely disposed in an engaging slot of a nozzle pipe device; wherein the spray assembly includes first nozzles disposed on an inside of the trough body and second nozzles disposed on an outside of the trough body, the first nozzles are configured to clean a feed machine and a clamping mushroom head, and the second nozzles are configured to clean a sheave of the outside of the trough body. An advantage of the present disclosure is changing manually cleaning to cleaning by a spray device, which drastically improves cleaning efficiency and also prevents influence of human factors to cleanliness of the machine.Type: ApplicationFiled: July 31, 2023Publication date: March 6, 2025Applicant: TCL ZHONGHUAN RENEWABLE ENERGY TECHNOLOGY CO., LTD.Inventors: Yannan LI, Pengfan BI, Chuanling AI, Yi SUN, Shaohua FU, Yue ZHANG, Hongxia CEN, Chao XIN, Hui WEI
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Patent number: 12243914Abstract: A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.Type: GrantFiled: July 26, 2022Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Lee-Chung Lu, Ting-Wei Chiang, Li-Chun Tien
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Patent number: 12242321Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: GrantFiled: April 27, 2023Date of Patent: March 4, 2025Assignee: ASUSTEK COMPUTER INC.Inventors: Wen Che Chung, Hui Chuan Lo, Hao-Hsuan Lin, Chun Tsao, Jun-Fu Chen, Ming-Hung Yao, Jia-Wei Zhang, Kuan-Lun Chen, Ting-Chao Lin, Cheng-Yen Lin, Chunyen Lai
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Patent number: 12243901Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.Type: GrantFiled: March 15, 2023Date of Patent: March 4, 2025Assignee: Artilux, Inc.Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
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Patent number: 12243810Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.Type: GrantFiled: November 16, 2022Date of Patent: March 4, 2025Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hui Min Ler, Soon Wei Wang, Chee Hiong Chew
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Publication number: 20250067385Abstract: Provided is a device for maintaining an equipment configured to maintain a to-be-maintained equipment (1). The to-be-maintained equipment (1) includes a first side and a second side opposite to the first side, and the device includes: at least one guide rail (3) extending in a first direction, wherein the first direction is a direction pointing from the first side to the second side; a sliding mechanism (4) arranged on the guide rail (3) and configured to support the to-be-maintained equipment (1); and a driving mechanism (5) configured to drive the sliding mechanism (4) and the to-be-maintained equipment (1) to move along the guide rail (3), wherein the device is configured to allow the to-be-maintained equipment (1) to move along the guide rail (3) to change a maintenance space on the first side or the second side.Type: ApplicationFiled: September 29, 2022Publication date: February 27, 2025Inventors: Qingping HUANG, Yong ZHOU, Hui DING, Baoyuan HU, Bintao WEI
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Patent number: 12234543Abstract: A method for preparing bismuth oxide nanowire films by heating in an upside down position includes: washing a substrate, and fixing the substrate to a substrate support in a magnetron sputtering system in a position where an electrically conductive surface of the substrate faces downwards; placing a bismuth target, which is adhered to a copper backing plate, on a sputtering head in the magnetron sputtering system; performing direct current magnetron sputtering to form a bismuth film on the electrically conductive surface of the substrate; and regulating a heating temperature to maintain the bismuth film in a semi-molten state, and providing a predetermined oxygen gas concentration to form the bismuth oxide nanowire film.Type: GrantFiled: August 18, 2020Date of Patent: February 25, 2025Assignee: Institute of Analysis. Guangdong Academy of Sciences (China National Analytical Center, Guangzhou)Inventors: Fuxian Wang, Liling Wei, Qiong Liu, Hui Cheng
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Publication number: 20250062503Abstract: A battery, relating to the technical field of batteries, is used for solving the technical problem that a first connector of the battery is easy to deform in a process of battery assembly and installation. The battery includes a housing, a first connector, a first adapter and a supporting block. After connecting the first connector to the housing, the supporting block is correspondingly arranged at the first connector. The supporting block is matched with an accommodating part formed by the first connector so as to provide supporting function for the first connector. The battery provided by the present application has a simple structure, and may avoid deformation of the first connector during the welding of the first adapter and the first connector of the battery.Type: ApplicationFiled: November 6, 2024Publication date: February 20, 2025Inventors: Jinyong ZHOU, Zhida Wei, Jichun Xie, Chengbei Li, Hui Zhang, Yang Xi
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Publication number: 20250061260Abstract: An integrated circuit includes a plurality of routing lines extending along a first direction, the plurality of routing lines being separated in the first direction by integral multiples of a nominal minimum pitch. The integrated circuit includes a plurality of standard cells, at least one of the plurality of standard cells having a first boundary coinciding with a routing line of the plurality of routing lines, and a second boundary offset from each of the plurality of routing lines.Type: ApplicationFiled: November 5, 2024Publication date: February 20, 2025Inventors: Shang-Chih HSIEH, Chun-Fu CHEN, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Hsiang-Jen TSENG
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Publication number: 20250062195Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.Type: ApplicationFiled: November 5, 2024Publication date: February 20, 2025Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
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Patent number: 12230603Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.Type: GrantFiled: July 26, 2023Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Wei Chan, Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Lee
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Patent number: 12232425Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: GrantFiled: November 21, 2023Date of Patent: February 18, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Patent number: D1063054Type: GrantFiled: August 3, 2022Date of Patent: February 18, 2025Assignee: DELTA ELECTRONICS, INC.Inventors: Hui-Lun Chin, Chih-Wei Chan, Ching-Hsien Yeh, Che-Wei Lee
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Patent number: D1063055Type: GrantFiled: August 3, 2022Date of Patent: February 18, 2025Assignee: DELTA ELECTRONICS, INC.Inventors: Hui-Lun Chin, Chih-Wei Chan, Ching-Hsien Yeh, Che-Wei Lee
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Patent number: D1063056Type: GrantFiled: August 3, 2022Date of Patent: February 18, 2025Assignee: DELTA ELECTRONICS, INC.Inventors: Hui-Lun Chin, Chih-Wei Chan, Ching-Hsien Yeh, Che-Wei Lee