Patents by Inventor Hui-Wen Lin
Hui-Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9978853Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.Type: GrantFiled: March 13, 2017Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
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Publication number: 20180019133Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: ApplicationFiled: September 27, 2017Publication date: January 18, 2018Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Patent number: 9779947Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: January 6, 2016Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin
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Publication number: 20170186853Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
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Patent number: 9595443Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.Type: GrantFiled: October 20, 2011Date of Patent: March 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Zhu, Hui-Wen Lin, Harry-Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
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Patent number: 9577051Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width. Each gate electrode of the first set of gate electrodes has a first gate width. The method further includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width. Each gate electrode of the second set of gate electrodes has a second gate width greater than the first gate width.Type: GrantFiled: June 20, 2014Date of Patent: February 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lee-Wee Teo, Ming Zhu, Hui-Wen Lin, Bao-Ru Young, Harry-Hak-Lay Chuang
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Publication number: 20160196979Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: ApplicationFiled: January 6, 2016Publication date: July 7, 2016Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Patent number: 9252224Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: August 28, 2014Date of Patent: February 2, 2016Assignee: Taiwan semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Harry-Hak-Lay Chuang
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Patent number: 9219124Abstract: A semiconductor device including a first gate structure associated with a first type of transistor and a second gate structure of a second type of transistor. The first gate structure includes a capping layer, a first metal layer having a first type of work function on the capping layer, and a second metal layer having a second type of work function, overlying the first metal layer and a fill layer on the second metal layer. The second type of work function is different than the first type of work function. The second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and the fill layer on the second metal layer.Type: GrantFiled: June 27, 2014Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak Lay Chuang, Ming Zhu, Hui Wen Lin, Bao Ru Young
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Publication number: 20140374835Abstract: A semiconductor device including a first gate structure associated with a first type of transistor and a second gate structure of a second type of transistor. The first gate structure includes a capping layer, a first metal layer having a first type of work function on the capping layer, and a second metal layer having a second type of work function, overlying the first metal layer and a fill layer on the second metal layer. The second type of work function is different than the first type of work function. The second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and the fill layer on the second metal layer.Type: ApplicationFiled: June 27, 2014Publication date: December 25, 2014Inventors: Harry-Hak Lay Chuang, Ming Zhu, Hui Wen Lin, Bao Ru Young
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Publication number: 20140367802Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: ApplicationFiled: August 28, 2014Publication date: December 18, 2014Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, JUNG-HUI KAO, Yuan-Tien Tu, HUAN-JUST LIN, Chih-Tang Peng, Pei-Ren Jeng, BAO-RU YOUNG, HARRY-HAK-LA Y CHUANG
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Publication number: 20140299937Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width. Each gate electrode of the first set of gate electrodes has a first gate width. The method further includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width. Each gate electrode of the second set of gate electrodes has a second gate width greater than the first gate width.Type: ApplicationFiled: June 20, 2014Publication date: October 9, 2014Inventors: Lee-Wee TEO, Ming ZHU, Hui-Wen LIN, Bao-Ru YOUNG, Harry-Hak-Lay CHUANG
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Patent number: 8822283Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: September 24, 2011Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
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Patent number: 8772147Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes.Type: GrantFiled: September 20, 2013Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Wee Teo, Ming Zhu, Hui-Wen Lin, Bao-Ru Young, Harry-Hak-Lay Chuang
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Patent number: 8772114Abstract: A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.Type: GrantFiled: March 30, 2012Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hak-Lay Chuang, Ming Zhu, Hui-Wen Lin, Bao-Ru Young
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Publication number: 20140017886Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes.Type: ApplicationFiled: September 20, 2013Publication date: January 16, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lee-Wee TEO, Ming ZHU, Hui-Wen LIN, Bao-Ru YOUNG, Harry-Hak-Lay CHUANG
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Patent number: 8557659Abstract: The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.Type: GrantFiled: October 5, 2012Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Wee Teo, Ming Zhu, Hui-Wen Lin, Bao-Ru Young, Harry-Hak-Lay Chuang
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Publication number: 20130256805Abstract: A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.,Inventors: Hak-Lay Chuang, Ming Zhu, Hui-Wen Lin, Bao-Ru Young
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Publication number: 20130099323Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming ZHU, Hui-Wen LIN, Harry-Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN
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Patent number: RE45060Abstract: The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.Type: GrantFiled: April 11, 2013Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Wee Teo, Ming Zhu, Hui-Wen Lin, Bao-Ru Young, Harry-Hak-Lay Chuang