Patents by Inventor Hui-Wen Miao

Hui-Wen Miao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8787434
    Abstract: A sampling phase selection method for a data stream is provided, wherein the data stream has a variable data rate in a fixed time period. The method comprises generating a calibration signal, wherein the time interval of the calibration signal is longer than the fixed time period of the data stream, generating a first clock sequence and a subsequent second clock sequence, wherein the first and the second clock sequence are composed of a plurality of continuous clock phases and the number of the clock phases of the first clock sequence are the same as that of the clock phases of the second clock sequence, selecting one of the phases of the first and the second clock sequence, in turn, to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, and selecting a final sampling phase according to the flag signals with different sampling phases.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: July 22, 2014
    Assignee: Raydium Semiconductor Corporation
    Inventors: Ren-Feng Huang, Hui Wen Miao, Ko-Yang Tso, Chin-Chieh Chao
  • Patent number: 8786641
    Abstract: A digital-to-analog (D/A) converter comprises a decoder apparatus and an operational amplifier. The decoder apparatus comprises first and second decoder unit. The first decoder unit selects a voltage of first voltage set as first and second voltage in response to a value of first gray level set. The second decoder unit selects first border voltage of second voltage set as the first and the second voltages and second border voltage of that as the first and the second voltages in response to the maximum and the minimum value of second gray level set respectively. The second decoder unit further selects the first and the second boarder voltage as the first and the second voltage respectively in response to an intermediate value of the second gray level set. The operational amplifier generates a pixel voltage having level between the first and the second voltage accordingly.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: July 22, 2014
    Assignee: Raydium Semiconductor Corporation
    Inventors: Ko-Yang Tso, Hui-Wen Miao, Chin-Chieh Chao
  • Patent number: 8767899
    Abstract: The current disclosure discloses a sampling phase selection method for a data stream, wherein the data stream has a variable data rate in a fixed time period. The method comprises the following steps: generating M section signals with the same time interval during the fixed time period of the data stream, generating N continuous clock phases according to a rising edge of each of the section signals, selecting one of the continuous clock phases corresponding to the different section signals in turn to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, repeating the selecting and the sampling steps to generate N flag signals corresponding to the different section signals, and selecting a final sampling phase according to the N flag signals corresponding to the different section signals.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: July 1, 2014
    Assignee: Raydium Semiconductor Corporation
    Inventors: Ren-Feng Huang, Hui Wen Miao, Ko-Yang Tso, Chin-Chieh Chao
  • Patent number: 8742967
    Abstract: An analog to digital converter generating a number of corresponding voltages in response to a number of values of a grey level is provided. The analog to digital converter includes a decoder and an operational amplifier. The decoder provides first to third output voltages having the same level when w most significant bits (MSBs) of the grey level correspond to the same value, provides first and second intermediate voltages in response to the x MSBs next to the w MSBs when the w MSBs correspond to different values, and selectively has the first to the third output voltages equal to one of the first and the second intermediate voltages. The operational amplifier obtains a pixel voltage by interpolating the first to the third output voltages, wherein the sum of w and x is smaller than or equal to the bit number of the gray level.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: June 3, 2014
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chien-Ming Chen, Hui-Wen Miao, Ko-Yang Tso
  • Patent number: 8736372
    Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 27, 2014
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chien-Ming Chen, Yann-Hsiung Liang, Hui-Wen Miao, Ko-Yang Tso
  • Patent number: 8736373
    Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 27, 2014
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chien-Ming Chen, Yann-Hsiung Liang, Hui-Wen Miao, Ko-Yang Tso
  • Patent number: 8659332
    Abstract: A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 25, 2014
    Assignee: Raydium Semiconductor Corporation
    Inventors: Ko-Yang Tso, Hui-Wen Miao, Yann-Hsiung Liang, Chin-Chieh Chao, Ren-Feng Huang
  • Publication number: 20140002290
    Abstract: An analog to digital converter generating a number of corresponding voltages in response to a number of values of a grey level is provided. The analog to digital converter includes a decoder and an operational amplifier. The decoder provides first to third output voltages having the same level when w most significant bits (MSBs) of the grey level correspond to the same value, provides first and second intermediate voltages in response to the x MSBs next to the w MSBs when the w MSBs correspond to different values, and selectively has the first to the third output voltages equal to one of the first and the second intermediate voltages. The operational amplifier obtains a pixel voltage by interpolating the first to the third output voltages, wherein the sum of w and x is smaller than or equal to the bit number of the gray level.
    Type: Application
    Filed: June 18, 2013
    Publication date: January 2, 2014
    Inventors: Chien-Ming Chen, Hui-Wen Miao, Ko-Yang Tso
  • Patent number: 8594263
    Abstract: A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: November 26, 2013
    Assignee: Raydlum Semiconductor Corporation
    Inventors: Ren-Feng Huang, Hui Wen Miao, Ko-Yang Tso, Chin-Chieh Chao
  • Patent number: 8542277
    Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 24, 2013
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chih-Chuan Huang, Hui-Wen Miao, Ko-Yang Tso
  • Patent number: 8542038
    Abstract: A source driver and a receiver thereof are disclosed. A two-stage amplifier of the receiver includes a first-stage circuit and a second-stage circuit. The second-stage circuit includes a first switch, a second switch, a third switch, a first node, and a second node. The first switch is coupled between the first node and a ground end; the second switch is coupled between the second node and the ground end; the third switch is coupled between the first node and the second node. When the receiver wants to wake up from a power-saving mode to a normal operation mode, the first switch and the second switch are switched to the off-state according to a control signal at first; after a period of delay time, the third switch is also switched to the off-state according to a delayed control signal.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: September 24, 2013
    Assignee: Raydium Semiconductor Corporation
    Inventors: Ren-Feng Huang, Hui-Wen Miao, Ko-Yang Tso
  • Publication number: 20130241623
    Abstract: A level shift circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a latch-type level shifter, a first current source and a second current source. The first input terminal receives an input signal; the second input terminal receives an inverse signal of the input signal; the first output terminal outputs an output signal; and the second output terminal outputs an inverse signal of the output signal. The latch-type level shifter is connected to the first input terminal, the second input terminal, the first output terminal and the second output terminal. The first current source is connected between a first high voltage input terminal of the latch-type level shifter and a voltage source. The second current source is connected between a second high voltage input terminal of the latch-type level shifter and the voltage source.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 19, 2013
    Applicant: RAYDIUM SEMICONDUCTOR CORPORATION
    Inventors: YU CHUN LIN, HUI WEN MIAO
  • Publication number: 20130058445
    Abstract: The current disclosure discloses a sampling phase selection method for a data stream, wherein the data stream has a variable data rate in a fixed time period. The method comprises the following steps: generating M section signals with the same time interval during the fixed time period of the data stream, generating N continuous clock phases according to a rising edge of each of the section signals, selecting one of the continuous clock phases corresponding to the different section signals in turn to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, repeating the selecting and the sampling steps to generate N flag signals corresponding to the different section signals, and selecting a final sampling phase according to the N flag signals corresponding to the different section signals.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 7, 2013
    Applicant: RAYDIUM SEMICONDUCTOR CORPORATION
    Inventors: REN-FENG HUANG, HUI WEN MIAO, KO-YANG TSO, CHIN-CHIEH CHAO
  • Publication number: 20120280966
    Abstract: A flicker suppression device applied in a display driver for preventing the output image data of the display driver from being affected by an electrostatic discharge (ESD) event is provided. The flicker suppression device includes an ESD detector and an output stage controller. The ESD detector is coupled to a first power wire of the display driver for determining whether an ESD level shift event occurs to the first system reference voltage signal on the first power wire. If so, a control signal corresponding to the first level is provided. The output stage controller controls the output stage circuit of the display driver to be in a high impedance state in response to the control signal corresponding to the first level to avoid the output stage circuit outputting an output image data that has been affected by an ESD event.
    Type: Application
    Filed: April 4, 2012
    Publication date: November 8, 2012
    Applicant: RAYDIUM SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Chen, Hui-Wen Miao, Ko-Yang Tso
  • Publication number: 20120269308
    Abstract: A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 25, 2012
    Applicant: RAYDIUM SEMICONDUCTOR CORPORATION
    Inventors: REN-FENG HUANG, HUI WEN MIAO, KO-YANG TSO, CHIN-CHIEH CHAO
  • Publication number: 20120256660
    Abstract: A source driver and a receiver thereof are disclosed. A two-stage amplifier of the receiver includes a first-stage circuit and a second-stage circuit. The second-stage circuit includes a first switch, a second switch, a third switch, a first node, and a second node. The first switch is coupled between the first node and a ground end; the second switch is coupled between the second node and the ground end; the third switch is coupled between the first node and the second node. When the receiver wants to wake up from a power-saving mode to a normal operation mode, the first switch and the second switch are switched to the off-state according to a control signal at first; after a period of delay time, the third switch is also switched to the off-state according to a delayed control signal.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 11, 2012
    Inventors: Ren-Feng Huang, Hui-Wen Miao, Ko-Yang Tso
  • Publication number: 20120249245
    Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Inventors: Chien-Ming Chen, Yann-Hsiung Liang, Hui-Wen Miao, Ko-Yang Tso
  • Publication number: 20120249244
    Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Inventors: Chien-Ming Chen, Yann-Hsiung Liang, Hui-Wen Miao, Ko-Yang Tso
  • Patent number: 8233253
    Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: July 31, 2012
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chih-Chuan Huang, Hui-Wen Miao, Ko-Yang Tso
  • Publication number: 20120176168
    Abstract: A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 12, 2012
    Applicant: RAYDIUM SEMICONDUCTOR CORPORATION
    Inventors: Ko-Yang Tso, Hui-Wen Miao, Yann-Hsiung Liang, Chin-Chieh Chao, Ren-Feng Huang