Patents by Inventor Hui-Yin Seto
Hui-Yin Seto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8819354Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.Type: GrantFiled: June 16, 2005Date of Patent: August 26, 2014Assignee: LSI CorporationInventors: Hui-Yin Seto, Derrick Sai-Tang Butt, Cheng-Gang Kong
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Patent number: 8516425Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.Type: GrantFiled: July 9, 2012Date of Patent: August 20, 2013Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20120278783Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 8239813Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.Type: GrantFiled: June 30, 2011Date of Patent: August 7, 2012Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 8230143Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.Type: GrantFiled: April 1, 2005Date of Patent: July 24, 2012Assignee: LSI CorporationInventors: Hui-Yin Seto, Cheng-Gang Kong
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Publication number: 20110258587Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 7996804Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: GrantFiled: January 17, 2008Date of Patent: August 9, 2011Assignee: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykih, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 7605628Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.Type: GrantFiled: May 7, 2007Date of Patent: October 20, 2009Assignee: LSI CorporationInventors: Terence J. Magee, Thomas Hughes, Hui-Yin Seto
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Publication number: 20090187873Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 7525356Abstract: A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.Type: GrantFiled: September 14, 2006Date of Patent: April 28, 2009Assignee: LSI CorporationInventors: Keven Hui, Ting Fang, Hui Yin Seto
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Publication number: 20080278210Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.Type: ApplicationFiled: May 7, 2007Publication date: November 13, 2008Inventors: Terence J. Magee, Thomas Hughes, Hui-Yin Seto
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Patent number: 7443741Abstract: A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for each of the one or more datapaths based upon actual memory accesses and (C) delaying a read data strobe signal based upon the base delay and the optimum offset delay value for each of the one or more datapaths.Type: GrantFiled: July 7, 2005Date of Patent: October 28, 2008Assignee: LSI CorporationInventors: Derrick Sai-Tang Butt, Hui-Yin Seto
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Patent number: 7394707Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.Type: GrantFiled: June 24, 2005Date of Patent: July 1, 2008Assignee: LSI CorporationInventors: Hui-Yin Seto, Derrick Sai-Tang Butt
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Publication number: 20080068060Abstract: A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Inventors: Keven Hui, Ting Fang, Hui Yin Seto
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Patent number: 7215584Abstract: A method for calibrating read data strobe gating including the steps of: (A) performing a coarse timing adjustment configured to determine a coarse delay setting that produces invalid data, (B) performing a medium timing adjustment configured to adjust a medium delay setting and the coarse delay setting until valid data is detected, (C) performing a fine timing adjustment configured to adjust the medium delay setting and a fine delay setting until valid data is detected and (D) adding one-half cycle to a gating delay determined by the coarse, the medium and the fine delay settings.Type: GrantFiled: July 1, 2005Date of Patent: May 8, 2007Assignee: LSI Logic CorporationInventors: Derrick Sai-Tang Butt, Hui-Yin Seto
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Publication number: 20070008791Abstract: A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for each of the one or more datapaths based upon actual memory accesses and (C) delaying a read data strobe signal based upon the base delay and the optimum offset delay value for each of the one or more datapaths.Type: ApplicationFiled: July 7, 2005Publication date: January 11, 2007Inventors: Derrick Butt, Hui-Yin Seto
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Publication number: 20070002642Abstract: A method for calibrating read data strobe gating including the steps of: (A) performing a coarse timing adjustment configured to determine a coarse delay setting that produces invalid data, (B) performing a medium timing adjustment configured to adjust a medium delay setting and the coarse delay setting until valid data is detected, (C) performing a fine timing adjustment configured to adjust the medium delay setting and a fine delay setting until valid data is detected and (D) adding one-half cycle to a gating delay determined by the coarse, the medium and the fine delay settings.Type: ApplicationFiled: July 1, 2005Publication date: January 4, 2007Inventors: Derrick Butt, Hui-Yin Seto
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Publication number: 20060291302Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.Type: ApplicationFiled: June 24, 2005Publication date: December 28, 2006Inventors: Hui-Yin Seto, Derrick Butt
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Publication number: 20060288175Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.Type: ApplicationFiled: June 16, 2005Publication date: December 21, 2006Inventors: Hui-Yin Seto, Derrick Butt, Cheng-Gang Kong
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Publication number: 20060224847Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.Type: ApplicationFiled: April 1, 2005Publication date: October 5, 2006Inventors: Hui-Yin Seto, Cheng-Gang Kong