Patents by Inventor Hui-Yun Chao
Hui-Yun Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10161965Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.Type: GrantFiled: March 16, 2015Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Long Chen, Chien-Chih Liao, Chin-Hsiang Lin, Hui-yun Chao, Jong-I Mou, Tseng Chin Lo, Ta-Yung Lee
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Patent number: 9165843Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.Type: GrantFiled: January 16, 2015Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Long Chen, Hui-Yun Chao, Yen-Di Tsen, Jong-I Mou
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Patent number: 9158867Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.Type: GrantFiled: October 9, 2012Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsien Lin, Jui-Long Chen, Hui-Yun Chao, Jong-I Mou, Chin-Hsiang Lin
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Publication number: 20150192616Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.Type: ApplicationFiled: March 16, 2015Publication date: July 9, 2015Inventors: Jui-Long Chen, Chien-Chih Liao, Chin-Hsiang Lin, Hui-yun Chao, Jong-I Mou, Tseng Chin Lo, Ta-Yung Lee
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Publication number: 20150125970Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.Type: ApplicationFiled: January 16, 2015Publication date: May 7, 2015Inventors: Jui-Long CHEN, Hui-Yun CHAO, Yen-Di TSEN, Jong-I MOU
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Patent number: 9000798Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.Type: GrantFiled: June 13, 2012Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Long Chen, Chien-Chih Liao, Tseng Chin Lo, Hui-Yun Chao, Ta-Yung Lee, Jong-I Mou, Chin-Hsiang Lin
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Patent number: 8942840Abstract: A system and method for manufacturing semiconductor devices is disclosed. An embodiment comprises using desired device parameters to choose an initial manufacturing recipe. Once chosen, the initial manufacturing recipe may be modified by determining and applying an offset adjustment based on previous manufacturing to tune the recipes for the particular equipment to be utilized in the manufacturing process.Type: GrantFiled: January 16, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Long Chen, Hui-Yun Chao, Chia-Tong Ho
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Patent number: 8938698Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.Type: GrantFiled: December 17, 2013Date of Patent: January 20, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Long Chen, Hui-Yun Chao, Yen-Di Tsen, Jong-I Mou
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Publication number: 20140106474Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Long CHEN, Hui-Yun CHAO, Yen-Di TSEN, Jong-I MOU
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Publication number: 20140100684Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Chun-Hsien Lin, Jui-Long Chen, Hui-Yun Chao, Jong-I Mou, Chin-Hsiang Lin
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Patent number: 8627251Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.Type: GrantFiled: April 25, 2012Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Long Chen, Hui-Yun Chao, Yen-Di Tsen, Jong-I Mou
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Publication number: 20130335109Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Long Chen, Chien-Chih Liao, Tseng Chin Lo, Hui-Yun Chao, Ta-Yung Lee, Jong-I Mou, Chin-Hsiang Lin
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Publication number: 20130288403Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.Type: ApplicationFiled: April 25, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Long CHEN, Hui-Yun CHAO, Yen-Di TSEN, Jong-I MOU
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Patent number: 8406912Abstract: System and method for data mining and feature tracking for fab-wide prediction and control are described. One embodiment is a system comprising a database for storing raw wafer manufacturing data; a data mining module for processing the raw wafer manufacturing data to select the best data therefrom in accordance with at least one of a plurality of knowledge-, statistic-, and effect-based processes; and a feature tracking module associated with the data mining module and comprising a self-learning model wherein a sensitivity of the self-learning model is dynamically tuned to meet real-time production circumstances, the feature tracking module receiving the selected data from the data mining module and generating prediction and control data therefrom; wherein the prediction and control data are used to control future processes in the wafer fabrication facility.Type: GrantFiled: June 25, 2010Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Long Chen, Chia-Tong Ho, Po-Feng Tsai, Hui-Yun Chao, Jong-I Mou
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Patent number: 8391999Abstract: A system and method for manufacturing semiconductor devices is disclosed. An embodiment comprises using desired device parameters to choose an initial manufacturing recipe. Once chosen, the initial manufacturing recipe may be modified by determining and applying an offset adjustment based on previous manufacturing to tune the recipes for the particular equipment to be utilized in the manufacturing process.Type: GrantFiled: June 9, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Long Chen, Hui-Yun Chao, Chia-Tong Ho
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Publication number: 20110320026Abstract: System and method for data mining and feature tracking for fab-wide prediction and control are described. One embodiment is a system comprising a database for storing raw wafer manufacturing data; a data mining module for processing the raw wafer manufacturing data to select the best data therefrom in accordance with at least one of a plurality of knowledge-, statistic-, and effect-based processes; and a feature tracking module associated with the data mining module and comprising a self-learning model wherein a sensitivity of the self-learning model is dynamically tuned to meet real-time production circumstances, the feature tracking module receiving the selected data from the data mining module and generating prediction and control data therefrom; wherein the prediction and control data are used to control future processes in the wafer fabrication facility.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Long Chen, Chia-Tong Ho, Po-Feng Tsai, Hui-Yun Chao, Jong-I Mou
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Publication number: 20110307088Abstract: A system and method for manufacturing semiconductor devices is disclosed. An embodiment comprises using desired device parameters to choose an initial manufacturing recipe. Once chosen, the initial manufacturing recipe may be modified by determining and applying an offset adjustment based on previous manufacturing to tune the recipes for the particular equipment to be utilized in the manufacturing process.Type: ApplicationFiled: June 9, 2010Publication date: December 15, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Long Chen, Hui-Yun Chao, Chia-Tong Ho