Patents by Inventor Hui-Zhong ZHUANG

Hui-Zhong ZHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210004518
    Abstract: A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Kuang-Ching CHANG, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Jung-Chan YANG
  • Publication number: 20210005633
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Publication number: 20210005634
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 10885254
    Abstract: A method of manufacturing an integrated circuit includes manufacturing a first set of conductive features by a first mask, positioning a set of gates in a second direction, manufacturing a second set of conductive features by a second mask, and electrically coupling a first portion of the set of gates to a second portion of the set of gates. The first and second set of conductive features is in a first direction and a first layer. The set of gates is in a second layer. The first portion of the set of gates corresponds to a gate terminal of a first n-type transistor, the second portion of the set of gates corresponds to a gate terminal of a first p-type transistor, the first n-type transistor being part of a first transmission gate, and the first p-type transistor being part of a second transmission gate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien
  • Patent number: 10879229
    Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
  • Publication number: 20200402979
    Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
    Type: Application
    Filed: May 20, 2020
    Publication date: December 24, 2020
    Inventors: Shao-Lun Chien, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue
  • Publication number: 20200402968
    Abstract: A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.
    Type: Application
    Filed: April 22, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Zhong ZHUANG, Xiang-Dong CHEN, Lee-Chung LU, Tzu-Ying LIN, Yung-Chin HOU
  • Patent number: 10867099
    Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10867104
    Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a third type-one transistor, and a fourth type-one transistor. The first type-one transistor and the third type-one transistor are in the first portion of the type-one active zone. The integrated circuit includes a first type-two transistor in the first portion of the type-two active zone. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a gate configured to have the first supply voltage of a second power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 15, 2020
    Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Jerry Chang Jui Kao, Yu-Ti Su, Wei-Hsiang Ma, Jiun-Jia Huang
  • Patent number: 10867114
    Abstract: An integrated circuit (IC) structure includes a first active region, a second active region, a first multi-gate structure, a first rail and a second rail. The first active region and the second active region extend in a first direction and are located at a first level. The second active region is separated from the first active region in a second direction. The first multi-gate structure extends in the second direction, overlaps the first active region and the second active region, and is located at a second level different from the first level. The first rail extends in the first direction, overlaps a portion of the first active region, supplies a first supply voltage, and is located at a third level. The second rail extends in the first direction, is located at the third level, is separated from the first rail in the second direction, and supplies a second supply voltage.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Zhong Zhuang, Ting-Wei Chiang, Lee-Chung Lu, Li-Chun Tien, Shun Li Chen
  • Patent number: 10868008
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: December 15, 2020
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Patent number: 10867100
    Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10867986
    Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shun-Li Chen, Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Jung-Chan Yang
  • Patent number: 10854499
    Abstract: An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Cheng-I Huang, Hui-Zhong Zhuang, Chi-Yu Lu, Stefan Rusu
  • Publication number: 20200357793
    Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Kam-Tou SIO, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Yi-Hsun CHIU
  • Publication number: 20200350250
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chih-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Ya-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Publication number: 20200335489
    Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Publication number: 20200328210
    Abstract: An integrated circuit includes a first transistor, a second transistor, and a first insulating layer. The first transistor is disposed in a first layer and comprises a first gate. The second transistor is disposed in a second layer above the first layer and comprises a second gate. The first gate and second gate are separated from each other in a first direction. The first insulating layer is disposed between the first gate of the first transistor and the second gate of the second transistor. The first insulating layer is configured to electrically insulate the first gate of the first transistor from the second gate of the second transistor.
    Type: Application
    Filed: March 2, 2020
    Publication date: October 15, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei WU, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20200328201
    Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 15, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Sing LI, Guo-Huei WU, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20200327273
    Abstract: An IC device includes a gate structure including an isolation layer laterally adjacent to a gate electrode, a transistor including a first S/D structure, a second S/D structure, and a channel extending through the gate electrode, a third S/D structure overlying the first S/D structure, a fourth S/D structure overlying the second S/D structure, and a conductive structure overlying the isolation layer and configured to electrically connect the third S/D structure to the fourth S/D structure.
    Type: Application
    Filed: March 31, 2020
    Publication date: October 15, 2020
    Inventors: Shih-Wei PENG, Guo-Huei WU, Wei-Cheng LIN, Hui-Zhong ZHUANG, Jiann-Tyng TZENG