Patents by Inventor Hui-Zhong ZHUANG

Hui-Zhong ZHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12015409
    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
  • Patent number: 12014982
    Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yu Lin, Jung-Chan Yang, Hui-Zhong Zhuang, Sheng-Hsiung Chen, Kuo-Nan Yang, Chih-Liang Chen, Lee-Chung Lu
  • Patent number: 12009362
    Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai, Shang-Wen Chang
  • Patent number: 12009824
    Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang, Chi-Lin Liu
  • Patent number: 11995390
    Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang, Yu-Ti Su, Wei-Hsiang Ma
  • Patent number: 11990477
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 11983479
    Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Publication number: 20240153940
    Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: SHUN-LI CHEN, CHUNG-TE LIN, HUI-ZHONG ZHUANG, PIN-DAI SUE, JUNG-CHAN YANG
  • Publication number: 20240153942
    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Patent number: 11979158
    Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yu Lin, Yung-Chen Chien, Jia-Hong Gao, Jerry Chang Jui Kao, Hui-Zhong Zhuang
  • Publication number: 20240143888
    Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active region extend in a first direction, and are on a first level. The first active region includes a first and second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact includes a first and second portion. The first portion overlaps the first and second drain/source. The second portion overlaps the first contact, the first and third drain/source region, and the first insulating region, and is electrically coupled to the first portion, and electrically insulated from the first drain/source region.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Pochun WANG, Yu-Jung CHANG, Hui-Zhong ZHUANG, Ting-Wei CHIANG
  • Publication number: 20240145481
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: POCHUN WANG, GUO-HUEI WU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, LI-CHUN TIEN
  • Patent number: 11973110
    Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Yuan Chang, Hui-Zhong Zhuang, Chih-Liang Chen
  • Patent number: 11967596
    Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 11948886
    Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20240104288
    Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
  • Publication number: 20240105555
    Abstract: A semiconductor device includes first and second gate structures, a metallization layer, and first and second tie-off contacts. The first and second gate structures extend substantially along a first direction and are aligned with each other substantially along the first direction. The metallization layer includes a Vdd line, a Vss line, metal lines between the Vdd line and the Vss line and extending substantially along a second direction different from the first direction. The first tie-off contact overlaps an intersection of the first gate structure and a first one of the Vdd line and the Vss line from a top view. The second tie-off contact overlaps an intersection of the second gate structure and a first one of the metal lines from the top view, wherein said first one of the metal lines is adjacent to a second one of the Vdd line and the Vss line.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Satyabrata DASH, Jian-Sing LI, Hui-Zhong ZHUANG
  • Publication number: 20240105726
    Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 28, 2024
    Inventors: Shao-Lun Chien, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue
  • Patent number: 11942420
    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG