Patents by Inventor Hui-Zhong ZHUANG

Hui-Zhong ZHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT
    Publication number: 20200320244
    Abstract: An integrated circuit structure includes a first, a second and a third set of conductive structures and a first and a second set of vias. The first set of conductive structures extend in a first direction, and is located at a first level. The second set of conductive structures extends in a second direction, overlaps the first set of conductive structures, and is located at a second level. The first set of vias is between, and electrically couples the first and the second set of conductive structures. The third set of conductive structures extends in the first direction, overlaps the second set of conductive structures, covers a portion of the first set of conductive structures, and is located at a third level. The second set of vias is between, and electrically couples the second and the third set of conductive structures.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Lee-Chung LU, Li-Chun TIEN, Meng-Hung SHEN, Shang-Chih HSIEH, Chi-Yu LU
  • Hybrid fin field-effect transistor cell structures and related methods
    Patent number: 10797078
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • METHOD AND SYSTEM FOR GENERATING LAYOUT DIAGRAM FOR SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS
    Publication number: 20200302101
    Abstract: A method of manufacturing a semiconductor device (for a layout diagram stored on a non-transitory computer-readable medium) includes generating the layout diagram. The generating the layout diagram includes: placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area; selecting a first pitch for additional cells to be placed in the spare region, wherein use of the first pitch minimizes wasted space in the spare region; selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and placing the selected SNYP spare cells into the spare region of the layout diagram.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Mao-Wei CHIU, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Li-Chun TIEN, Chi-Yu LU
  • Method for improved cut metal patterning
    Patent number: 10783313
    Abstract: A method of preparing an integrated circuit device design including analyzing a preliminary device layout to identify a vertical abutment between a first cell and a second cell, the locations of, and spacing between, internal metal cuts within the first and second cells, indexing the second cell relative to the first cell by N CPP to define one or more intermediate device layouts to define a modified device layout with improved internal metal cut spacing in order to suppress BGE and LE.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuang-Ching Chang, Ting-Wei Chiang, Hui-Zhong Zhuang, Jung-Chan Yang
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20200286919
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Inventors: HSUEH-CHIH CHOU, CHIA HAO TU, SANG HOO DHONG, LEE-CHUNG LU, LI-CHUN TIEN, TING-WEI CHIANG, HUI-ZHONG ZHUANG
  • LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT
    Publication number: 20200285797
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • METAL CUT OPTIMIZATION FOR STANDARD CELLS
    Publication number: 20200285792
    Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheok-Kei LEI, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chi-Yu LU, Yi-Hsin KO
  • Cell Layout and Structure
    Publication number: 20200257842
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 13, 2020
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Integrated circuit, system for and method of forming an integrated circuit
    Patent number: 10740531
    Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Integrated circuit, system for and method of forming an integrated circuit
    Patent number: 10734377
    Abstract: An integrated circuit structure includes a first well, and a first and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion. The second portion extends in the first direction and has a second width greater than the first width. The first set of implants are in the first portion of the first well, and the second set of implants are in the second portion of the first well. At least one implant of the first set of implants being configured to be coupled to a first supply voltage. Each implant of the second set of implants having a second dopant type different from a first dopant type of the first set of implants.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
  • Integrated circuit and method of manufacturing same
    Patent number: 10734321
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Semiconductor device and layout design thereof
    Patent number: 10727177
    Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue
  • Integrated circuit layout and method of configuring the same
    Patent number: 10707199
    Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Metal cut optimization for standard cells
    Patent number: 10691849
    Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
  • Semiconductor structure
    Patent number: 10685982
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Li-Chun Tien, Ting-Wei Chiang, Hui-Zhong Zhuang
  • Layout for integrated circuit and the integrated circuit
    Patent number: 10685162
    Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Semiconductor device having engineering change order (ECO) cells
    Patent number: 10678977
    Abstract: A semiconductor device including: standard functional cells located in a logic area; standard spare cells arranged in a spare region of the logic area; and a metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; and wherein a first pitch of the standard spare cells is based on a second pitch of the strap lines.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Chi-Yu Lu
  • Cell layout and structure
    Patent number: 10664639
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • MULTI-BIT STANDARD CELL
    Publication number: 20200151297
    Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.
    Type: Application
    Filed: July 25, 2019
    Publication date: May 14, 2020
    Inventors: JERRY CHANG JUI KAO, HUI-ZHONG ZHUANG, YUNG-CHEN CHIEN, TING-WEI CHIANG, CHIH-WEI CHANG, XIANGDONG CHEN
  • INTEGRATED CIRCUIT LAYOUTS WITH SOURCE AND DRAIN CONTACTS OF DIFFERENT WIDTHS
    Publication number: 20200135869
    Abstract: A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.
    Type: Application
    Filed: September 24, 2019
    Publication date: April 30, 2020
    Inventors: Shang-Syuan Ciou, Hui-Zhong Zhuang, Jung-Chan Yang, Li-Chun Tien