Abstract: A semiconductor device, comprising at least one active region; at least one MD region formed over a portion of the at least one active region; and at least one gate electrode formed over a portion of the at least one active region different than the portion of the active region where the MD region is formed. The semiconductor device further comprises at least one metal layer over at least a portion of the at least one active region, the at least one metal layer being located on a layer of the semiconductor device, different than the layers on which the at least one MD region and at least one gate electrode are formed. A via is formed over the at least one active region and configured to connect one of the at least one gate electrodes to one of the at least one metal layers. The at least one metal layer is configured to enable the at least one gate electrode to be connected to another at least one electrode and/or at least one MD region.

Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

Abstract: A system and method of layout design for an integrated circuit and integrated circuit, the method includes positioning all conductive traces of a first mask pattern, in a first direction, wherein the conductive traces of the first mask pattern are in a first conductive layer. The method also includes positioning all conductive traces of a second mask pattern, in the first direction, wherein the conductive traces of the second mask pattern are in the first conductive layer, and the second mask pattern is offset from the first mask pattern in a second direction different from the first direction.

Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An example circuit includes: one or more power rails and a tap cell structure. The tap cell structure includes one or more decoupling capacitor cells and one or more tap cells. The one or more tap cells are electrically coupled to the one or more power rails. The one or more decoupling capacitor cells are disposed adjacent to the tap cells and electrically coupled to the one or more power rails.

Abstract: An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.

Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.

Abstract: An integrated circuit layout includes a first metal line, a second metal line, at least one first conductive via and a first conductive segment. The first metal line is formed along a first direction. The at least one first conductive via is disposed over the first metal line. The second metal line is disposed over at least one first conductive via and is in parallel with the first metal line. The first conductive segment is formed on one end of the second metal line.

Abstract: In some embodiments, a flip-flop is laid-out on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made of a first plurality of devices which are circumscribed by a master switch perimeter residing within the flip-flop region. Scan mux input circuitry is operably coupled to an input of the master switch circuitry. The scan mux input circuitry is made up of a second plurality of devices that are circumscribed by a scan mux perimeter which resides within the flip-flop region and which is non-overlapping with the master switch perimeter. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter which resides within the flip-flop region and which is non-overlapping with both the master switch perimeter and the scan mux perimeter.

Abstract: A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.

Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.

Abstract: A layout of a cell grid comprises a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged horizontally and evenly spaced with a pitch X, and a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged vertically and evenly spaced with a pitch Y, wherein the pitch Y of the fin-shaped OD regions defines width of the cell grid. The layout of the cell grid further comprises a plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in the fin-shaped OD regions and their gates connected to the POLY lines, wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated by a first carve-out region, and a conductive feature over the first carve-out region and electrically connecting the first portion and the second portion of the first gate electrode.