Patents by Inventor Huibin CHEN

Huibin CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118617
    Abstract: A power module includes a first substrate, a second substrate, a first heat sink, a second heat sink, and a chip that are disposed opposite to each other. The chip is disposed between the first heat sink and the second heat sink that are disposed opposite to each other. The first heat sink and the second heat sink are connected to the chip through sintering or welding. The first substrate and the second substrate are respectively connected to the first heat sink and the second heat sink through welding or sintering.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventors: Huibin CHEN, Jiyang LI, Heng WANG
  • Patent number: 12251820
    Abstract: A pneumatic soft grabbing sensing device includes a support; a flexible grabbing mechanism including at least two flexible claws, wherein the at least two flexible claws are arranged on the support in a circumferential direction, each flexible claw includes a telescopic air bag, an adapter mechanism and a flexible plate connected with the adapter mechanism, the telescopic air bag is hollow and elongated, the telescopic air bag includes a closed end, an open end and an air bag main body connected between the closed end and the open end, the air bag main body includes at least two air bag bodies and a node portion formed between adjacent air bag bodies, and the adapter mechanism is connected to the node portion, the closed end and open end; and a sensing mechanism including at least two sensing parts, the sensing parts being arranged on inner sides of the corresponding flexible plates.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: March 18, 2025
    Assignee: SOOCHOW UNIVERSITY
    Inventors: Tao Chen, Zhiwei Dai, Minglu Zhu, Huibin Jia, Lining Sun
  • Publication number: 20250079387
    Abstract: A power module includes: a first metal brazed substrate; a chipset disposed on the first metal brazed substrate, where the chipset includes at least two chips; and a clip, where the clip covers a side, away from the first metal brazed substrate, of the chipset. Each connecting unit is electrically connected to a corresponding chip. Every two adjacent connecting units are connected along a first direction through a body. Each connecting arm is arranged with respect to two adjacent chips in the chipset. The connecting arm is connected to the first metal brazed substrate. A shortest distance between the connecting arm and one of the two adjacent chips is a first shortest distance, a shortest distance between the connecting arm and the other of the two adjacent chips is a second shortest distance. A difference between the first shortest distance and the second shortest distance falls within a preset threshold.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 6, 2025
    Inventors: Hui LI, Sizhan Zhou, Zhaoyue Wang, Huibin Chen, Huaibin Zhao, Junhe Wang, Yafei LV
  • Publication number: 20250070055
    Abstract: A power module includes a first metal layer-coated substrate, a plurality of chips, and a first connection piece. A first electrode of each chip is electrically connected to a first metal layer of the first metal layer-coated substrate. The first connection piece includes a first main body part and a plurality of first contact parts. A second electrode of each of the plurality of chips is in contact with at least one of the first contact parts. A part of the first main body part is between at least one pair of adjacent first contact parts. A current flowing out from the chip directly flows to the first main body part through the first contact part. The chips are connected in parallel by using the first connection piece.
    Type: Application
    Filed: November 10, 2024
    Publication date: February 27, 2025
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Fengqun Lang, Hui Li, Sizhan Zhou, Haiyan Liu, Huibin Chen, Zhen Lv, Chunfu HU
  • Publication number: 20250044486
    Abstract: A liquid lens controlled by an interdigital electrode made of two insulated wires includes an inner core cavity body, the two insulated wires, a first transparent body, a second transparent body, a first fluid, and a second fluid. The insulated wires are arranged side by side and longitudinally winded on the inner core cavity body; the insulated wires are configured to form an interdigital electrode on a sidewall of the inner core cavity body; the first transparent body is disposed at an upper end of the inner core cavity body and the second transparent body is disposed at a lower end of the inner core cavity body; a lens cavity is defined among the inner core cavity body, the first transparent body, and the second transparent body; the first fluid and the second fluid are immiscible, and disposed in the lens cavity.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 6, 2025
    Inventors: Tao Chen, Qingyu Hu, Xiuting Shang, Jingyi Sun, Lingcheng Gu, Ke Ding, Huibin Liu, Xiaoyu Zhang, Rongqing Xu
  • Publication number: 20250015616
    Abstract: Provided is a charging apparatus supporting a bidirectional switching circuit. The apparatus includes a connector housing, a connection body, and a wire. The connector housing has a T-shaped structure. The bottom of the connector housing in a vertical direction is fixed to one end of the connection body. The wire is fixed to another end of the connector body. A Type-C interface is installed on one end of the connector housing. A lightning interface is installed on another end of the connector housing. A chip is installed inside the connector housing.
    Type: Application
    Filed: July 1, 2024
    Publication date: January 9, 2025
    Applicant: XIEXUN ELECTRONIC(JIAN) CO.,LTD
    Inventors: Huibin CHEN, Shaopu WANG, Wenliang YIN, Wuhua ZHANG
  • Publication number: 20240354482
    Abstract: In the field of power module technologies, a method and an apparatus for designing a substrate of a power module and a terminal device may be provided. The method includes: obtaining input parameters for designing the substrate of the power module; determining types of basic layout units and a quantity of basic layout units of each type in a circuit topology based on information about the circuit topology and a prestored diagram of a structure of each type of basic layout unit; and connecting, by using a pathfinding model, a connection path of graph elements of each basic layout unit in the circuit topology, to obtain a connection diagram of the substrate of the power module.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 24, 2024
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Wuhua LI, Yu ZHOU, Haoze LUO, Sheng ZHENG, Sizhan ZHOU, Huibin CHEN
  • Patent number: 12119576
    Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: October 15, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie Chang, Huibin Chen, Tiburcio Maldo, Keunhyuk Lee
  • Publication number: 20240312895
    Abstract: A power module is provided that may include a first metal-clad substrate, a chip located on a side of the first metal-clad substrate, and first solder located between the first metal-clad substrate and the chip. A first metal layer is disposed on a surface that is of the first metal-clad substrate and that faces the chip, and the first metal layer includes a groove and a blocking part. A first thickness of the first metal layer is less than a second thickness. The first thickness is a thickness of at least a part of an area in the blocking part, and the second thickness is a thickness of the first metal layer in an area other than the groove and the blocking part. The blocking part is located between the chip and the adjacent groove, and is configured to prevent the first solder from overflowing into the groove.
    Type: Application
    Filed: May 23, 2024
    Publication date: September 19, 2024
    Inventors: Huibin Chen, Yutao Wang, Haiyan Liu, Song Chen, Zhonghua Yin, Zhen Lv, Zhaoyue Wang, Qiliang Yang
  • Publication number: 20240222231
    Abstract: A semiconductor die includes an electronic device formed in the semiconductor die. The semiconductor die further includes a plurality of device contact pads disposed on a surface of the semiconductor die. The plurality of device contact pads are electrically connected to the electronic device. The plurality of device contact pads include at least an emitter contact pad and a signal sense contact pad, and a dummy device contact pad disposed on the surface of the semiconductor die. The dummy device contact pad provides an area for a solder joint between the semiconductor die and a substrate in addition to an area provided by the plurality of device contact pads.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng LIN, Jerome TEYSSEYRE, Huibin CHEN
  • Publication number: 20240170439
    Abstract: A power module includes a first metal layer-clad substrate and a second metal layer-clad substrate that are disposed opposite to each other, and a chip and an interconnection pillar that are located between the first metal layer-clad substrate and the second metal layer-clad substrate. The chip and the first metal layer-clad substrate are electrically connected through press sintering by using a sintering material to improve bonding reliability. The chip is electrically connected to the second metal layer-clad substrate by using the interconnection pillar.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Fengqun Lang, Yutao Wang, Huibin Chen
  • Patent number: 11935817
    Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: March 19, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Jerome Teysseyre, Huibin Chen
  • Publication number: 20240006330
    Abstract: The present disclosure relates to a semiconductor arrangement, comprising: a substrate; a first group of semiconductor elements forming a first switch; a second group of semiconductor elements forming a second switch. The substrate comprises: a first electrically conductive area; a second electrically conductive area; a third electrically conductive area; a fourth electrically conductive area. The semiconductor arrangement further comprises: a first electrical connection line; a second electrical connection line; and a third electrical connection line. The first electrical connection line, the second electrical connection line, the third electrical connection line and the fourth area of the substrate are dimensioned according to a symmetry criterion to enable a simultaneous current flow through the load paths of the semiconductor elements of the first group as well as a simultaneous current flow through the load paths of the semiconductor elements of the second group.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 4, 2024
    Inventors: Juergen HOEGERL, Ruoyang Du, Huibin Chen
  • Publication number: 20230395556
    Abstract: A packaged structure includes a first substrate and a second substrate. Power units are disposed on a first surface of the first substrate. A control unit is disposed on a first surface of the second substrate, and the second substrate is connected to one end of the first substrate. The control unit is electrically connected to the power units. The control unit is configured to: receive an external input signal, collect an internal sensing signal, and control the power units to work. The first surface of the second substrate is disposed on a same side as the first surface of the first substrate. When the structure is used, a signal part and a power part are integrated. The power units are disposed on the first substrate, and the control unit is disposed on the second substrate, so that the signal part and the power part can be separately disposed.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 7, 2023
    Inventors: Zhihua Liu, Huibin Chen
  • Publication number: 20230268251
    Abstract: An encapsulation structure of a power module is disclosed in this application, which includes a power module and a liquid cooler. The power module includes a power module body, a metal baseplate, and heat dissipation finned tubes. A front side of the metal baseplate is connected to the power module body, and a back side of the metal baseplate is connected to the heat dissipation finned tubes. The metal baseplate has a protrusion part protruding. There are a plurality of grooves on a fluid pipe of the liquid cooler, a cavity exists between two adjacent grooves of the plurality of grooves, and the cavity is configured to communicate the two adjacent grooves. The power module body is lapped on the groove, a back side of the protrusion part is in contact with an edge surface of the groove, and the heat dissipation finned tubes are placed in the groove.
    Type: Application
    Filed: August 9, 2022
    Publication date: August 24, 2023
    Inventors: Huibin Chen, Haiyan Liu
  • Publication number: 20230230928
    Abstract: A substrate, a packaged structure, and an electronic device are provided. The substrate is configured to be electrically connected to a chip. The chip includes a power terminal and a signal terminal. The substrate includes a first substrate and a second substrate mounted on the first substrate. The first substrate includes a first layout, and the first layout is configured to be electrically connected to the power terminal. The second substrate includes a second layout, and the second layout is configured to be electrically connected to the signal terminal. A spacing between lines of the second layout is less than a spacing between lines of the first layout. The substrate provided in this application has a small size and high integration.
    Type: Application
    Filed: March 24, 2023
    Publication date: July 20, 2023
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Huibin Chen, Yongzhao Lin, Zhen Lv
  • Patent number: 11594510
    Abstract: In a general aspect, a method for producing a semiconductor device assembly can include defining a cavity in a conductive spacer, and electrically and thermally coupling a semiconductor die with the conductive spacer, such that the semiconductor die is at least partially embedded in the cavity. The semiconductor die can have a first surface having active circuitry included therein, a second surface opposite the first surface, and a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die. The method can also include electrically coupling a direct bonded metal (DBM) substrate with the first surface of the semiconductor die.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: February 28, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yong Liu, Yusheng Lin, Huibin Chen
  • Patent number: 11127651
    Abstract: In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 21, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie Chang, HuiBin Chen, Keunhyuk Lee, Jerome Tysseyre
  • Publication number: 20210225797
    Abstract: In a general aspect, a method for producing a semiconductor device assembly can include defining a cavity in a conductive spacer, and electrically and thermally coupling a semiconductor die with the conductive spacer, such that the semiconductor die is at least partially embedded in the cavity. The semiconductor die can have a first surface having active circuitry included therein, a second surface opposite the first surface, and a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die. The method can also include electrically coupling a direct bonded metal (DBM) substrate with the first surface of the semiconductor die.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yong LIU, Yusheng LIN, Huibin CHEN
  • Patent number: 10991670
    Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor die having a first surface including active circuitry, a second surface opposite the first surface, and a plurality of side surfaces. Each of the plurality of side surfaces can extend between the first surface of the semiconductor die and the second surface of the semiconductor die. The semiconductor device assembly can also include a conductive spacer having a cavity defined therein. The semiconductor die can be electrically and thermally coupled with the conductive spacer, the semiconductor die being at least partially embedded in the cavity.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 27, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yong Liu, Yusheng Lin, Huibin Chen