Patents by Inventor HuiChang Moon

HuiChang Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11871571
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: January 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Publication number: 20220359566
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 11387249
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 12, 2022
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Publication number: 20220059567
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: November 2, 2021
    Publication date: February 24, 2022
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Publication number: 20220037355
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: October 8, 2021
    Publication date: February 3, 2022
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Publication number: 20200111811
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 9, 2020
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 10546872
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Publication number: 20170301690
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 9735170
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 15, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Publication number: 20160111440
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 21, 2016
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 9245839
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: January 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 8933505
    Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunghoi Hur, Jinho Kim, Sunil Shim, Su-Youn Yi, HuiChang Moon
  • Publication number: 20140015128
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Publication number: 20130248983
    Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.
    Type: Application
    Filed: May 20, 2013
    Publication date: September 26, 2013
    Inventors: Younggoan Jang, Sunghoi Hur, Jinho Kim, Sunil Shim, Su-Youn Yi, HuiChang Moon
  • Patent number: 8541831
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
  • Patent number: 8445954
    Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younggoan Jang, Sunghoi Hur, Jinho Kim, Sunil Shim, Su-Youn Yi, HuiChang Moon
  • Patent number: 8107289
    Abstract: A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: January 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunil Shim, Sunghoi Hur, Younggoan Jang, Jinho Kim, Su-Youn Yi, HuiChang Moon
  • Publication number: 20110305083
    Abstract: A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 15, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunil Shim, Sunghoi Hur, Younggoan Jang, Jinho Kim, Su-Youn Yi, HuiChang Moon
  • Patent number: 8027197
    Abstract: A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: September 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunil Shim, Sunghoi Hur, Younggoan Jang, Jinho Kim, Su-Youn Yi, HuiChang Moon
  • Publication number: 20100133599
    Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 3, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho