Patents by Inventor HuiChang Moon
HuiChang Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240164103Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: January 22, 2024Publication date: May 16, 2024Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20240155840Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 11871571Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: GrantFiled: November 2, 2021Date of Patent: January 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20220359566Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 11387249Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: GrantFiled: December 10, 2019Date of Patent: July 12, 2022Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20220059567Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20220037355Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: October 8, 2021Publication date: February 3, 2022Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20200111811Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: December 10, 2019Publication date: April 9, 2020Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 10546872Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: GrantFiled: June 27, 2017Date of Patent: January 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20170301690Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: June 27, 2017Publication date: October 19, 2017Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 9735170Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: GrantFiled: December 17, 2015Date of Patent: August 15, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20160111440Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: December 17, 2015Publication date: April 21, 2016Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 9245839Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: GrantFiled: September 16, 2013Date of Patent: January 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 8933505Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.Type: GrantFiled: May 20, 2013Date of Patent: January 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sunghoi Hur, Jinho Kim, Sunil Shim, Su-Youn Yi, HuiChang Moon
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Publication number: 20140015128Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Publication number: 20130248983Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.Type: ApplicationFiled: May 20, 2013Publication date: September 26, 2013Inventors: Younggoan Jang, Sunghoi Hur, Jinho Kim, Sunil Shim, Su-Youn Yi, HuiChang Moon
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Patent number: 8541831Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.Type: GrantFiled: December 3, 2009Date of Patent: September 24, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Soodoo Chae, Myoungbum Lee, HuiChang Moon, Hansoo Kim, JinGyun Kim, Kihyun Kim, Siyoung Choi, Hoosung Cho
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Patent number: 8445954Abstract: A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.Type: GrantFiled: November 24, 2009Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Younggoan Jang, Sunghoi Hur, Jinho Kim, Sunil Shim, Su-Youn Yi, HuiChang Moon
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Patent number: 8107289Abstract: A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.Type: GrantFiled: August 25, 2011Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sunil Shim, Sunghoi Hur, Younggoan Jang, Jinho Kim, Su-Youn Yi, HuiChang Moon
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Publication number: 20110305083Abstract: A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.Type: ApplicationFiled: August 25, 2011Publication date: December 15, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sunil Shim, Sunghoi Hur, Younggoan Jang, Jinho Kim, Su-Youn Yi, HuiChang Moon