Patents by Inventor Hui-Chong Shin
Hui-Chong Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10684979Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.Type: GrantFiled: November 1, 2019Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
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Publication number: 20200065289Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.Type: ApplicationFiled: November 1, 2019Publication date: February 27, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-young Lim, Hui-chong Shin, ln-su Choi, Young-ho Lee
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Patent number: 10496584Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.Type: GrantFiled: March 9, 2018Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
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Publication number: 20180329850Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.Type: ApplicationFiled: March 9, 2018Publication date: November 15, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
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Patent number: 9520160Abstract: A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved.Type: GrantFiled: March 28, 2014Date of Patent: December 13, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chil-Nam Yoon, Seon-Ryeong Kang, Hui-Chong Shin
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Publication number: 20140301125Abstract: A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved.Type: ApplicationFiled: March 28, 2014Publication date: October 9, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: CHIL-NAM YOON, SEON-RYEONG KANG, HUI-CHONG SHIN
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Patent number: 7814379Abstract: A memory module packaging test system may include a plurality of test slots into which a plurality of memory modules may be installed so that the system may simultaneously test the memory modules. The memory module packaging test system may use a server system for a registered dual in-line memory module (RDIMM) or a fully buffered dual in-line memory module (FBDIMM) so that the system may test an unbuffered dual in-line memory module (UDIMM).Type: GrantFiled: June 20, 2007Date of Patent: October 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-kuk Lee, You-keun Han, Hui-chong Shin
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Patent number: 7606110Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.Type: GrantFiled: January 5, 2005Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: You-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Byung-Se So, Young-Man Ahn, Seung-Man Shin, Jung-Kuk Lee, Ho-Suk Lee
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Patent number: 7519873Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.Type: GrantFiled: September 8, 2006Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Seung-Jin Seo, You-Keun Han, Hui-Chong Shin, Jong-Geon Lee, Kyung-Hee Han
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Publication number: 20080016400Abstract: A memory module packaging test system may include a plurality of test slots into which a plurality of memory modules may be installed so that the system may simultaneously test the memory modules. The memory module packaging test system may use a server system for a registered dual in-line memory module (RDIMM) or a fully buffered dual in-line memory module (FBDIMM) so that the system may test an unbuffered dual in-line memory module (UDIMM).Type: ApplicationFiled: June 20, 2007Publication date: January 17, 2008Inventors: Jung-kuk Lee, You-keun Han, Hui-chong Shin
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Publication number: 20070030814Abstract: A memory module and method thereof are provided. In the example method, a test signal may be applied to a plurality of memory chips included in the memory module. Output data from the plurality of memory chips may be received in response to the applied test signal. The received, output data may be divided into a plurality of groups. At least one of the plurality of groups may be selected in response to an output group selection signal. The at least one selected group may be output (e.g., to an external device). The example memory module may include a plurality of chips and a hub. The example memory module may be configured to perform the above-described example method.Type: ApplicationFiled: July 20, 2006Publication date: February 8, 2007Inventors: Seung-Man Shin, Hui-Chong Shin, Jong-Geon Lee, Kyung-Hee Han
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Publication number: 20070022335Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.Type: ApplicationFiled: September 8, 2006Publication date: January 25, 2007Inventors: Seung-Man Shin, Seung-Jin Seo, You-Keun Han, Hui-Chong Shin, Jong-Geon Lee, Kyung-Hee Han
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Publication number: 20060064611Abstract: A method of testing an integrated circuit includes providing a bank access sequence received to a register in the integrated circuit, generating a test pattern sequence based on the bank access sequence, and performing a Built-In Self Test (BIST) operation on the integrated circuit based on the generated test pattern sequence.Type: ApplicationFiled: September 16, 2005Publication date: March 23, 2006Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, Hui-Chong Shin
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Publication number: 20060044927Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.Type: ApplicationFiled: January 5, 2005Publication date: March 2, 2006Inventors: You-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Byung-Se So, Young-Man Ahn, Seung-Man Shin, Jung-Kuk Lee, Ho-Suk Lee
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Publication number: 20050289287Abstract: A method of entering memory module mounted on a memory system or a plurality of memories mounted on the memory module into a test mode, and a first register and a second register for performing the method are introduced. Each of the memory manufacturers provides a different MRS code for entering the memory into the test mode and a different method of entering the memory into the test mode from one another. As a result, the number of the test MRS is stored in the first register for controlling the memory, and the test MRS codes are programmed into the second register. Additionally, each of the bits stored in the first register used for determining the number of the test MRS corresponds to each of the second registers that store a corresponding test MRS code, respectively.Type: ApplicationFiled: June 2, 2005Publication date: December 29, 2005Inventors: Seung-Man Shin, Seung-Jin Seo, You-Keun Han, Hui-Chong Shin, Jong-Geon Lee, Kyung Han
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Patent number: 6883061Abstract: An electronic system having a plurality of dynamic semiconductor memory devices and a refresh method for the same. The system comprises a plurality of dynamic semiconductor memory devices and a controller. Each of the dynamic semiconductor memory devices includes a storage device for storing a designated number designating an order for performing a refresh operation, a refresh enable signal generating circuit for generating a refresh enable signal in response to a refresh control command supplied from the controller and a delaying circuit for delaying the refresh enable signal by different time intervals determined by the designated number.Type: GrantFiled: January 17, 2003Date of Patent: April 19, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Cheul Seo, Jin-Ho So, Hui-Chong Shin, Meoung-Cheol Nam
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Publication number: 20030145163Abstract: An electronic system having a plurality of dynamic semiconductor memory devices and a refresh method for the same. The system comprises a plurality of dynamic semiconductor memory devices and a controller. Each of the dynamic semiconductor memory devices includes a storage device for storing a designated number designating an order for performing a refresh operation, a refresh enable signal generating circuit for generating a refresh enable signal in response to a refresh control command supplied from the controller and a delaying circuit for delaying the refresh enable signal by different time intervals determined by the designated number.Type: ApplicationFiled: January 17, 2003Publication date: July 31, 2003Inventors: Jong-Cheul Seo, Jin-Ho So, Hui-chong Shin, Meoung-Cheol Nam