Patents by Inventor Hui-chul Shin

Hui-chul Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056587
    Abstract: A semiconductor device includes an active region defined by an element isolation region in a base substrate, source and drain regions of a first conductivity type spaced apart from each other, and formed in the active region, a body region of a second conductivity type surrounding the source region, and formed in the base substrate, a drift region of the first conductivity type surrounding the drain region, having a lower impurity concentration than the drain region, and formed in the base substrate, an insulating structure including a buried insulating pattern and a semiconductor pattern sequentially stacked on the drift region, a gate dielectric film including a first portion extending along an upper surface of the body region and a second portion extending along a side surface and an upper surface of the insulating structure, and a gate electrode extending along an upper surface of the gate dielectric film.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hui Chul Shin, Woo Yeol Maeng
  • Patent number: 10916648
    Abstract: An integrated circuit device includes a bulk substrate including a first conductivity type well and a second conductivity type drift region, a stack pattern disposed on the bulk substrate and including a buried insulation pattern on the second conductivity type drift region and a semiconductor body pattern on the buried insulation pattern, a gate insulation layer on an upper surface of the first conductivity type well and on a sidewall and an upper surface of the stack pattern, and a gate electrode on the gate insulation layer. The gate electrode includes a first gate portion opposite to the first conductivity type well with the gate insulation layer therebetween and a second gate portion opposite to the second conductivity type drift region with the gate insulation layer and the stack pattern therebetween.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-young Kim, Aliaksei Ivaniukovich, Hui-chul Shin, Mi-jin Han
  • Publication number: 20200335623
    Abstract: A semiconductor device includes an active region defined by an element isolation region in a base substrate, source and drain regions of a first conductivity type spaced apart from each other, and formed in the active region, a body region of a second conductivity type surrounding the source region, and formed in the base substrate, a drift region of the first conductivity type surrounding the drain region, having a lower impurity concentration than the drain region, and formed in the base substrate, an insulating structure including a buried insulating pattern and a semiconductor pattern sequentially stacked on the drift region, a gate dielectric film including a first portion extending along an upper surface of the body region and a second portion extending along a side surface and an upper surface of the insulating structure, and a gate electrode extending along an upper surface of the gate dielectric film.
    Type: Application
    Filed: November 26, 2019
    Publication date: October 22, 2020
    Inventors: HUI CHUL SHIN, WOO YEOL MAENG
  • Publication number: 20190386134
    Abstract: An integrated circuit device includes a bulk substrate including a first conductivity type well and a second conductivity type drift region, a stack pattern disposed on the bulk substrate and including a buried insulation pattern on the second conductivity type drift region and a semiconductor body pattern on the buried insulation pattern, a gate insulation layer on an upper surface of the first conductivity type well and on a sidewall and an upper surface of the stack pattern, and a gate electrode on the gate insulation layer. The gate electrode includes a first gate portion opposite to the first conductivity type well with the gate insulation layer therebetween and a second gate portion opposite to the second conductivity type drift region with the gate insulation layer and the stack pattern therebetween.
    Type: Application
    Filed: January 8, 2019
    Publication date: December 19, 2019
    Inventors: Kwan-young Kim, Aliaksei Ivaniukovich, Hui-chul Shin, Mi-jin Han