Abstract: Methods and apparatuses related to fiducial designs for fiducial markers on glass substrates, or other transparent or translucent substrates, are disclosed. Example fiducial designs can facilitate visual recognition by enhancing edge detection in visual perception. In example fiducial designs, optical features on glass substrates can re-direct light so as to present a bright image region. Such optical features can include surface relief patterns formed in a coating on the surface of glass substrates. An exemplary method for manufacturing the fiducial markers can involve transfers of a fiducial design across a master mold or plate, a submaster mold or plate, and a target glass substrate. A fiducial marker can facilitate the use of the substrate in a variety of applications, including machine vision systems that facilitate automated performance of manufacturing processes on input working material.

Abstract: Methods and systems for manufacturing an optical waveguide include depositing an adhesion promoting layer on a substrate. Multiple curable resist droplets are dispensed on the adhesion promoting layer. The adhesion promoting layer is disposed between and contacts the substrate and the curable resist droplets. The curable resist droplets define an optical eyepiece layer such that a zero residual layer thickness (RLT) region of the optical eyepiece layer is free of the curable resist droplets. The optical eyepiece layer is incised from the substrate to form the optical waveguide.

Abstract: Methods and apparatuses related to fiducial designs for fiducial markers on glass substrates, or other transparent or translucent substrates, are disclosed. Example fiducial designs can facilitate visual recognition by enhancing edge detection in visual perception. In example fiducial designs, optical features on glass substrates can re-direct light so as to present a bright image region. Such optical features can include surface relief patterns formed in a coating on the surface of glass substrates. An exemplary method for manufacturing the fiducial markers can involve transfers of a fiducial design across a master mold or plate, a submaster mold or plate, and a target glass substrate. A fiducial marker can facilitate the use of the substrate in a variety of applications, including machine vision systems that facilitate automated performance of manufacturing processes on input working material.

Abstract: Methods and systems for qualifying a multi-layered optical stack include providing the multi-layered optical stack including a first optical layer and a second optical layer. The first optical layer includes a first pair of fiducial marks and the second optical layer includes a second pair of fiducial marks Each of the first pair are spaced laterally from each of the second pair such that the first pair and the second pair are visible through the optical stack. A first angle defined between a first reference line connecting the first pair and a global reference line is determined. A second angle defined between a second reference line connecting the second pair and the global reference line is determined. The multi-layered optical stack is qualified for use in the optical projection system based on whether a difference between the first angle and the second angle is less than a predetermined threshold.

Abstract: Methods and apparatuses related to fiducial designs for fiducial markers on glass substrates, or other transparent or translucent substrates, are disclosed. Example fiducial designs can facilitate visual recognition by enhancing edge detection in visual perception. In example fiducial designs, optical features on glass substrates can re-direct light so as to present a bright image region. Such optical features can include surface relief patterns formed in a coating on the surface of glass substrates. An exemplary method for manufacturing the fiducial markers can involve transfers of a fiducial design across a master mold or plate, a submaster mold or plate, and a target glass substrate. A fiducial marker can facilitate the use of the substrate in a variety of applications, including machine vision systems that facilitate automated performance of manufacturing processes on input working material.

Abstract: Methods and systems for qualifying a multi-layered optical stack include providing the multi-layered optical stack including a first optical layer and a second optical layer. The first optical layer includes a first pair of fiducial marks and the second optical layer includes a second pair of fiducial marks Each of the first pair are spaced laterally from each of the second pair such that the first pair and the second pair are visible through the optical stack. A first angle defined between a first reference line connecting the first pair and a global reference line is determined. A second angle defined between a second reference line connecting the second pair and the global reference line is determined. The multi-layered optical stack is qualified for use in the optical projection system based on whether a difference between the first angle and the second angle is less than a predetermined threshold.

Abstract: A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area.

Abstract: An IC structure including: a first replacement gate stack for the pFET, the first replacement gate stack including: an interfacial layer in a first opening in the dielectric layer; a high-k layer over the interfacial layer in the first opening; a pFET work function metal layer over the high-k layer in the first opening; and a first gate electrode layer over the pFET work function metal layer and substantially filling the first opening; and a second replacement gate stack for the nFET, the second gate stack laterally adjacent to the first gate stack and including: the interfacial layer in a second opening in the dielectric layer; the high-k layer over the interfacial layer in the second opening; a nFET work function metal layer over the high-k layer in the second opening; and a second gate electrode layer over the nFET work function metal layer and substantially filling the second opening.

Abstract: A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area.

Abstract: After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.

Abstract: After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.

Abstract: Embodiments of the present disclosure provide a method of processing an integrated circuit (IC) structure for metal gate replacement, the method comprising: providing a structure including a first semiconductor fin and a second semiconductor fin positioned over a buried insulator layer of a silicon-on-insulator (SOI) substrate, and a gate structure positioned over the first and second semiconductor fins, wherein the gate structure includes a gate dielectric layer and a metal layer positioned over the gate dielectric layer; forming a planarizing resist over the first and second semiconductor fins, wherein the planarizing resist includes: a first organic planarizing layer (OPL), and a second OPL over the first OPL; removing a portion of the second OPL; removing an exposed portion of the first OPL and a portion of the metal layer positioned over the second semiconductor fin; and forming a replacement metal gate (RMG) over the gate dielectric layer.

Abstract: After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.

Abstract: After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.

Abstract: A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.

Abstract: A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.