Patents by Inventor Huije Ryu

Huije Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250176301
    Abstract: Provided are semiconductor devices including vertically stacked semiconductor elements, methods of manufacturing the same, and electronic devices including the same. The semiconductor device includes a first semiconductor element formed in a front-end-of-line process, a second semiconductor element formed in a back-end-of-line process, and an interlayer insulating layer provided between the first and second semiconductor elements and including an internal via structure connecting the first and second semiconductor elements to each other. The internal via structure includes a layer structure through which an upper surface of a first material layer and a lower surface of a second material layer are connected to each other.
    Type: Application
    Filed: August 21, 2024
    Publication date: May 29, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Junyoung KWON, Changhyun KIM, Huije RYU, Kyung-Eun BYUN, Minsu SEOL, Eunkyu LEE, Changseok LEE
  • Publication number: 20250176226
    Abstract: Provided are a semiconductor device including a two-dimensional material and a manufacturing method thereof. The semiconductor device includes a channel layer containing a two-dimensional semiconductor material, a source electrode and a drain electrode provided on both sides of the channel layer, respectively, a gate insulating layer provided on the channel layer between the source electrode and the drain electrode and including a two-dimensional insulating material, an interlayer provided between the channel layer and the gate insulating layer, and a gate electrode provided on the gate insulating layer.
    Type: Application
    Filed: September 19, 2024
    Publication date: May 29, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeon Cheol PARK, Huije RYU, Kyung-Eun BYUN, Minsu SEOL, Joungeun YOO, Eunkyu LEE, Yeonchoo CHO
  • Publication number: 20250142874
    Abstract: Provided is a semiconductor device including a substrate, a first vertical channel, a spacer, and a second vertical channel. The first vertical channel may have a sheet shape extending in a direction perpendicular to a surface of the substrate. The spacer may be provided at an end of the first vertical channel in an extension direction. The second vertical channel may be aligned with the first vertical channel on the spacer and have a sheet shape extending in a vertical direction.
    Type: Application
    Filed: May 10, 2024
    Publication date: May 1, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Changhyun KIM, Kyung-Eun BYUN, Minsu SEOL, Junyoung KWON, Huije RYU, Eunkyu LEE, Yeonchoo CHO
  • Publication number: 20250142907
    Abstract: A semiconductor device may include a substrate, a vertical channel, a gate electrode, and a conductive layer. The vertical channel may have a tube shape extending in a direction perpendicular to a surface of the substrate. The gate electrode may face the vertical channel with an outer insulating layer therebetween on an outer circumferential surface of the vertical channel. The conductive layer may face the vertical channel with an inner insulating layer therebetween on an inner circumferential surface of the vertical channel.
    Type: Application
    Filed: April 23, 2024
    Publication date: May 1, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Changhyun KIM, Kyung-Eun BYUN, Minsu SEOL, Junyoung KWON, Huije RYU, Eunkyu LEE, Yeonchoo CHO
  • Publication number: 20250142894
    Abstract: A semiconductor device may include a two-dimensional (2D) material layer extending in a first direction, a source electrode and a drain electrode each electrically connected to the 2D material layer, an insulating layer arranged on the 2D material layer, and a gate electrode arranged apart from the 2D material layer in a second direction perpendicular to the first direction, wherein the insulating layer includes a dopant.
    Type: Application
    Filed: June 24, 2024
    Publication date: May 1, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Huije RYU, Junyoung KWON, Changhyun KIM, Minsu SEOL
  • Publication number: 20250126886
    Abstract: Provided is a semiconductor device including a two-dimensional (2D) material. The semiconductor device may include a first channel including a first 2D material layer, a second channel apart from the first channel in a first direction and including a second 2D material layer, a common gate electrode between the first channel and the second channel, a first electrode and a second electrode apart from each other and respectively in contact with the first channel and the second channel, and a common electrode apart from the first electrode and the second electrode in a second direction intersecting the first direction and in contact with the first channel and the second channel. One of the first channel and the second channel may be an n-type channel and the other one may be a p-type channel.
    Type: Application
    Filed: October 16, 2024
    Publication date: April 17, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun BYUN, Minsu SEOL, Junyoung KWON, Huije RYU
  • Publication number: 20250107096
    Abstract: A memory device may include a gate electrode, a channel layer spaced apart from the gate electrode, a charge trap layer between the gate electrode and the channel layer, and a two-dimensional material layer arranged between the charge trap layer and the gate electrode. The two-dimensional material layer may include a material having an electron affinity of less than 1 eV.
    Type: Application
    Filed: February 19, 2024
    Publication date: March 27, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeonchoo CHO, Junyoung KWON, Huije RYU, Minsu SEOL
  • Publication number: 20250107160
    Abstract: A transistor including a semiconductor channel including a compound semiconductor, and a source electrode and a drain electrode each electrically connected to the semiconductor channel and each independently including a topological conductor, wherein the compound semiconductor and the topological conductor include at least one metal element in common.
    Type: Application
    Filed: April 3, 2024
    Publication date: March 27, 2025
    Inventors: Joonseok Kim, Sangwon KIM, CHANG SEOK LEE, Huije Ryu, KEUN WOOK SHIN
  • Publication number: 20250098390
    Abstract: A panel includes: a substrate, unit pixels arranged repeatedly on the substrate, and unit pixel circuits including a unit pixel circuit repeatedly arranged on the substrate and electrically connected to a unit pixel. Each unit pixel includes a red sub-pixel including a red optoelectronic element configured to display red color or detect red light, a green sub-pixel including a green optoelectronic element configured to display green color or detect green light, and a blue sub-pixel including a blue optoelectronic element configured to display blue color or detect blue light. Each unit pixel circuit includes a red pixel circuit electrically connected to the red optoelectronic element, a green pixel circuit electrically connected to the green optoelectronic element, and a blue pixel circuit electrically connected to the blue optoelectronic element. The red pixel circuit, the green pixel circuit, and the blue pixel circuit are stacked along a thickness direction of the substrate.
    Type: Application
    Filed: May 2, 2024
    Publication date: March 20, 2025
    Inventors: Joonseok KIM, Joonyun KIM, Huije RYU, Chang Seok LEE, Luhing HU
  • Publication number: 20240349490
    Abstract: A semiconductor memory device includes a bit line that extends in a first direction, semiconductor patterns disposed on the bit line and spaced apart from each other in the first direction and each including a first vertical part, a second vertical part, and a horizontal part, first and second word lines disposed on the horizontal part and respectively adjacent to the first and second vertical parts, and a semiconductor dielectric pattern disposed on the bit line and between the semiconductor patterns. The semiconductor dielectric pattern includes a lower capping pattern, sidewall dielectric patterns spaced apart from each other in the first direction on the lower capping pattern, an air gap between the sidewall dielectric patterns, and an upper capping pattern disposed on the sidewall dielectric patterns. Top surfaces of the sidewall dielectric patterns are at the same height as top surfaces of the first and second vertical parts.
    Type: Application
    Filed: November 3, 2023
    Publication date: October 17, 2024
    Inventors: Huije RYU, Hyungki CHO
  • Publication number: 20230337413
    Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.
    Type: Application
    Filed: November 7, 2022
    Publication date: October 19, 2023
    Inventors: MIN HEE CHO, MIN TAE RYU, Huije Ryu, SUNGWON YOO, Yongjin Lee, WONSOK LEE
  • Publication number: 20230307551
    Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.
    Type: Application
    Filed: January 4, 2023
    Publication date: September 28, 2023
    Inventors: Sungwon YOO, Yongseok KIM, Min Tae RYU, Huije RYU, Yongjin LEE, Wonsok LEE, Min Hee CHO
  • Publication number: 20230292490
    Abstract: A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.
    Type: Application
    Filed: December 15, 2022
    Publication date: September 14, 2023
    Inventors: Yongjin Lee, Yongseok Kim, Mintae Ryu, Huije Ryu, Sungwon Yoo, Wonsok Lee, Minhee Cho