Patents by Inventor Huijie DUAN

Huijie DUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay line circuits and semiconductor integrated circuits
    Patent number: 9467130
    Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: October 11, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Quanfeng Liu, Huijie Duan
  • Delay line circuits and semiconductor integrated circuits
    Patent number: 9432012
    Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: August 30, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Quanfeng Liu, Huijie Duan
  • DELAY LINE CIRCUITS AND SEMICONDUCTOR INTEGRATED CIRCUITS
    Publication number: 20150349766
    Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.
    Type: Application
    Filed: January 28, 2015
    Publication date: December 3, 2015
    Inventors: Quanfeng LIU, Huijie DUAN
  • DELAY LINE CIRCUITS AND SEMICONDUCTOR INTEGRATED CIRCUITS
    Publication number: 20150349765
    Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.
    Type: Application
    Filed: December 31, 2014
    Publication date: December 3, 2015
    Inventors: Quanfeng LIU, Huijie DUAN