Abstract: A computerized simulation validating method for a full-scale distribution network single phase-to-ground fault test is implemented by simulating a full-scale test system with external quantities being controlled to be conformant and validating the full-scale distribution network single phase-to-ground fault test based on a conformance check result between the internal quantities of the field testing and the internal quantities of the simulation testing. The simulation validating method for a full-scale distribution network single phase-to-ground fault test improves normalization and conformance of the full-scale distribution network ground fault test. The computerized simulation validating system, apparatus, and medium for a full-scale distribution network single phase-to-ground fault test also achieve the benefits noted above.

Abstract: A layout of a driving circuit, a semiconductor structure and a semiconductor memory are provided. The layout includes P-type transistors, N-type transistors and four test modules. The four test modules are distributed on both sides of the P-type transistors and the N-type transistors in an upper-lower symmetrical structure, and the P-type transistors and the N-type transistors have an upper-lower structure distribution in the middle of the four test modules.

Abstract: Embodiments of the present disclosure include a layout of a semiconductor structure, including: a column decoder, wherein the column decoder includes a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region, and a NAND gate region. The first P-type transistor region is located above the first N-type transistor region, the second P-type transistor region is located above the first P-type transistor region, and the second N-type transistor region is located above the second P-type transistor region; the NAND gate region is adjacent to the first P-type transistor region, the second P-type transistor region, and the first N-type transistor region.