Abstract: A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

Abstract: The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

Abstract: A patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.

Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.

Abstract: A patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

Abstract: A patch antenna unit and an antenna that relate to the field of communications technology wherein the patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

Abstract: A patch antenna unit and an antenna that relate to the field of communications technology wherein the patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

Abstract: The disclosure discloses an antenna-in-package structure, including a first substrate and a second substrate. A first surface of the first substrate includes a first patch antenna, the second substrate is connected to a second surface of the first substrate, and the second substrate is provided with a third surface and a fourth surface. The third surface includes a second patch antenna, and a projection of the second patch antenna on the first surface at least partially overlaps the first patch antenna. A cavity is disposed between the first substrate and the second substrate, and the second patch antenna is separated from the second surface by the cavity. The fourth surface includes a radio frequency element, and the radio frequency element sends and receives a radio frequency signal by using the first patch antenna and the second patch antenna.

Abstract: This application provides a chip package structure. The chip package structure includes: a substrate and a chip, and further includes: a heat dissipation ring fastened onto the substrate and a planar heat pipe radiator covering the heat dissipation ring. The substrate, the heat dissipation ring, and the planar heat pipe radiator form a space to enclose the chip. A first metal thin film is disposed on a surface, facing the chip, of the planar heat pipe radiator, and the chip is thermally coupled to the first metal thin film by using a sintered metal layer.

Abstract: The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.

Abstract: The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

Abstract: Example chip package structure and packaging methods are described. One example chip package structure includes: a redistribution layer (RDL) and a target chip including an active surface and a back surface, where the active surface of the target chip is connected to a first surface of the RDL. The example chip package structure further includes a substrate, where a first surface of the substrate is opposite to the back surface of the target chip. The example chip package structure further includes an interconnection channel that is located around the target chip. One end of the interconnection channel is connected to the first surface of the RDL, and the other end of the interconnection channel is connected to the first surface of the substrate.

Abstract: A patch antenna unit and an antenna that relate to the field of communications technology wherein the patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

Abstract: The invention discloses a packaging structure, including a substrate, a fan-out unit, and a wiring layer. The fan-out unit includes a first chip and a second chip. The first chip includes a first pin array, and the second chip includes a second pin array. The fan-out unit further includes a third pin array. The first pin array, the second pin array, and the third pin array are all disposed facing the substrate. The wiring layer bridges over between the first pin array and the second pin array, and is configured to connect each first pin in the first pin array to a corresponding second pin in the second pin array. The substrate is provided with a soldering pad that is electrically connected to a wiring layer in the substrate, and the third pin array is connected to the soldering pad.

Abstract: This application provides a chip packaging system, including multiple chips, a substrate, a heat dissipating component, and at least one thermoelectric refrigeration chip. A heat dissipating ring and a heat dissipating lid are provided on the heat dissipating component. One end of the heat dissipating ring is secured to the substrate, and the other end, opposite to the end secured to the substrate. The multiple chips are disposed in space enclosed by the substrate, the heat dissipating ring, and the heat dissipating lid, and all of the multiple chips are separated each other by using a thermal insulation material or by air. One surface of each of the at least one thermoelectric refrigeration chip is a hot end and the other surface thereof is a cold end. The cold end of each thermoelectric refrigeration chip is disposed on a side close to the multiple chips.

Abstract: The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.