Abstract: The present disclosure relates to task solving methods. One example method includes obtaining importance of each first scheduling constraint in a plurality of first scheduling constraints in a first linear-programming task, where the importance indicates a degree of contribution of the first scheduling constraint to reducing a time for solving the first linear-programming task. The plurality of first scheduling constraints are sampled based on the importance to obtain a subset of the obtained plurality of first scheduling constraints, where the importance is used to determine sampling probability of the first scheduling constraints. A second linear-programming task is constructed based on the subset of the plurality of first scheduling constraints. The second linear-programming task is solved to obtain a first solving result. A first solving result is used as an initial value of the first linear-programming task, and an initialized first linear-programming task is solved.

Abstract: An industrial programming method and apparatus, a device, a storage medium, and a program product are provided. In a programming scheme generation method, a programming device obtains a first group of constraints for a plurality of parameters in an industrial programming job. Further, the programming device constructs, based on the first group of constraints, a cut constraint associated with at least one integer parameter in the plurality of parameters, and constructs a second group of constraints based on the cut constraint and the first group of constraints, where a type of the at least one integer parameter in the second group of constraints is changed. The programming device determines values of the plurality of parameters based on the second group of constraints, to generate a programming scheme for the industrial programming job.

Abstract: An automatic test pattern generation-based circuit verification method, comprises: determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first CNF based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.