Abstract: A highly wear-resistant tile, and a conveyor belt having the highly wear-resistant tile, the conveyor belt including highly wear-resistant tiles (6) and a main body (7). The highly wear-resistant tiles (6) includes a tile main body (1). An upper portion of the tile main body (1) has two first holes (2) extending downward. Central axes of the two first holes (2) are in the same plane, and lower ends of the first holes (2) have a chamfered structure. A reference hole (3) extending upward is provided at a center position of a lower portion of the main body (1). Two sets of second holes (4) of identical shape and size are provided at a periphery of the reference hole (3) and are separated by 90°. Each set of the second holes (4) has a center line in the same plane as a center line of the reference hole (3). Lower ends of the reference hole (3) and second holes (4) have a chamfered structure.

Abstract: A highly wear-resistant tile, and a conveyor belt having the highly wear-resistant tile, the conveyor belt including highly wear-resistant tiles (6) and a main body (7). The highly wear-resistant tiles (6) includes a tile main body (1). An upper portion of the tile main body (1) has two first holes (2) extending downward. Central axes of the two first holes (2) are in the same plane, and lower ends of the first holes (2) have a chamfered structure. A reference hole (3) extending upward is provided at a center position of a lower portion of the main body (1). Two sets of second holes (4) of identical shape and size are provided at a periphery of the reference hole (3) and are separated by 90°. Each set of the second holes (4) has a center line in the same plane as a center line of the reference hole (3). Lower ends of the reference hole (3) and second holes (4) have a chamfered structure.

Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.

Abstract: A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.

Abstract: A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.