Patents by Inventor Hui-Ping Liu

Hui-Ping Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126327
    Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240074328
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 9004070
    Abstract: A tracheotomy tube set is provided with a tracheotomy tube including: a cannula including a connecting member at a proximal end and a bellows member joining to the connecting member, a balloon cuff formed proximal to a distal end of the cannula, a first wing extending from one side of one end of the balloon cuff, a second wing extending from the other side of one end of the balloon cuff, a first wedge balloon formed between the first wing and an insertion section between the balloon cuff and the distal end of the cannula, an opposite second wedge balloon formed between the second wing and the insertion section, and a line having one end communicating with both the first and second wedge balloons; and a fixation device including a split flange, a hole through the split flange, and two slots formed at both sides of the fixation device respectively.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: April 14, 2015
    Inventors: Mao-Tsun Wu, Chen Yang, Yen-Ni Hung, Hui-Ping Liu
  • Patent number: 8894700
    Abstract: An abdominal aortic stent includes a first sub-stent and a second sub-stent each having a front end. The circumference of the front end of each sub-stent is half of the circumference of the abdominal aorta. When the circumference is gradually reduced to a rear end of each sub-stent, it has entered one side of the bilateral femoral arteries. The rear ends of the sub-stents with full circumference of the cross-sectional area of the femoral artery are included therein. The first and second sub-stents are coated with external removable membrane to compress the sub-stents to generate smaller circumferences. When the removable membrane has been removed, the sub-stents are fully extended to reconstruct the vascular flow path.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 25, 2014
    Inventors: Po-Jen Ko, Ching-Yang Wu, Yun-Hen Liu, Hui-Ping Liu
  • Publication number: 20140007882
    Abstract: A tracheotomy tube set is provided with a tracheotomy tube including a cannula including a connecting member at a proximal end and a bellows member joining to the connecting member, a balloon cuff formed proximal to a distal end of the cannula, a first wing extending from one side of one end of the balloon cuff, a second wing extending from the other side of one end of the balloon cuff, a first wedge balloon formed between the first wing and an insertion section between the balloon cuff and the distal end of the cannula, an opposite second wedge balloon formed between the second wing and the insertion section, and a line having one end communicating with both the first and second wedge balloons; and a fixation device including a split flange, a hole through the flange, and two slots formed at both sides of the fixation device respectively.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: Mao-Tsun Wu, Chen Yang, Yen-Ni Hung, Hui-Ping Liu
  • Publication number: 20140012174
    Abstract: An adhesive bandage is provided with a support cup having an annular marking formed on a periphery of an outer surface; a circular cushion member fitted in the support cup; a sliding cup; a sliding disc in the sliding cup and engaged the cushion member, the sliding disc being capable of sliding into the support cup; and a resilient main body including a transparent dome for concealing the sliding cup, the cushion member, the sliding disc, and the support cup, a first adhesive strip extending from a periphery of the dome; a second adhesive strip, opposite the first adhesive strip, extending from the periphery of the dome; a hook and loop fabric fastener on ends of the first and second adhesive strips.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: Mao-Tsun Wu, Yen-Ni Hung, Chen Yang, Hui-Ping Liu
  • Publication number: 20130218258
    Abstract: An abdominal aortic stent includes a first sub-stent and a second sub-stent, each having a front end and the circumference of the front end of each sub-stent is half of the circumference of the abdominal aorta, and when the circumference is gradually reduced to a rear end of each sub-stent, it has entered one side of the bilateral femoral arteries, wherein the rear ends of the sub-stents with full circumference of the cross-sectional area of the femoral artery are included therein; the first and second sub-stents are coated with external removable membrane to compress the sub-stents to generate smaller circumferences, and when the membrane has been removed, the sub-stents are fully extended to reconstruct the vascular flow path.
    Type: Application
    Filed: March 18, 2013
    Publication date: August 22, 2013
    Inventors: Po-Jen Ko, Ching-Yang Wu, Yun-Hen Liu, Hui-Ping Liu
  • Publication number: 20110295357
    Abstract: An abdominal aortic stent includes a first sub-stent and a second sub-stent, each having a front end and the circumference of the front end of each sub-stent is half of the circumference of the abdominal aorta, and when the circumference is gradually reduced to a rear end of each sub-stent, it has entered one side of the bilateral femoral arteries, wherein the rear ends of the sub-stents with full circumference of the cross-sectional area of the femoral artery are included therein; the first and second sub-stents are coated with external removable membrane to compress the sub-stents to generate smaller circumferences, and when the membrane has been removed, the sub-stents are fully extended to reconstruct the vascular flow path.
    Type: Application
    Filed: May 31, 2010
    Publication date: December 1, 2011
    Inventors: Po-Jen Ko, Ching-Yang Wu, Yun-Hen Liu, Hui-Ping Liu
  • Patent number: 7919874
    Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: April 5, 2011
    Assignees: ChipMOS Technologies, ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Publication number: 20100187692
    Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
    Type: Application
    Filed: April 8, 2010
    Publication date: July 29, 2010
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Publication number: 20100187691
    Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
    Type: Application
    Filed: April 8, 2010
    Publication date: July 29, 2010
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Patent number: 7723853
    Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: May 25, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Publication number: 20080303174
    Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
    Type: Application
    Filed: August 22, 2008
    Publication date: December 11, 2008
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Patent number: 7436074
    Abstract: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 14, 2008
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Publication number: 20070013043
    Abstract: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.
    Type: Application
    Filed: December 13, 2005
    Publication date: January 18, 2007
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Patent number: 6256550
    Abstract: A manufacturing control and reporting method/system for manufacture of semiconductor devices comprises a system for loading a mechanical article handling device in a semiconductor manufacturing system, provides an automatic check-in and changing equipment status to an UP status, automatically checking whether the article handling system is empty, and for automatically changing the system status to an IDLE status. The system provides automatic check-in, and subsequent to processing of the workload by the plant provides track-out followed by automatically checking whether the article handling system is empty. Then the system checking whether a TE has arrived, and the system checks whether the TE has reloaded the article handling system.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: July 3, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Wen Feng Wu, Ming-Hsiu Hsieh, Pai-Lan Chen, Ching-Ren Chen, Hui-Ping Liu
  • Patent number: 6204553
    Abstract: A lead frame for a semiconductor package. The lead frame includes a die pad and a plurality of leads. One surface of the die pad supports a silicon chip while the other surface has a plurality of annular grooves all having the same geometric center. The inner lead portion of the leads surrounds the die pad, but the die pad and the leads are on different planar surfaces.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: March 20, 2001
    Assignee: Walsin Advanced Electronics Ltd.
    Inventors: Wen-Chun Liu, Hui-Ping Liu, Jung-Jie Liou, Yi-Hsiang Pan, Sheng-Tung Tsai