Patents by Inventor Huixian Lai
Huixian Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240047519Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.Type: ApplicationFiled: October 16, 2023Publication date: February 8, 2024Applicant: Fujian Jinhua Integrated Circuit Co., LtdInventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu
-
Patent number: 11824087Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.Type: GrantFiled: June 16, 2021Date of Patent: November 21, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu
-
Publication number: 20230363146Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Cheng Tung, Huixian LAI, Yi-Wang Jhan
-
Publication number: 20230345724Abstract: The present disclosure provides a semiconductor memory structure and a method of fabricating the same includes a substrate; at least one first groove disposed on an upper surface of the substrate, with an edge corner of a top portion of the first groove being arc-shaped; a first dielectric layer disposed along an inner wall of the first groove; a second dielectric layer formed on a surface of the first dielectric layer, to fill up the first groove, wherein a top portion of the first dielectric layer is lower than a top portion of the second dielectric layer and an upper surface of the substrate, and a first recess is formed between the second dielectric layer and the substrate; and a metal filling layer disposed in the first recess, to fill in a partial space of the first recess.Type: ApplicationFiled: December 8, 2022Publication date: October 26, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Huixian LAI, Li-Wei Feng
-
Patent number: 11765886Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.Type: GrantFiled: August 9, 2021Date of Patent: September 19, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Cheng Tung, Huixian Lai, Yi-Wang Jhan
-
Publication number: 20230282248Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and at least one second word line arranged by a second pitch, and the second pitch is greater than the first pitch.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yifei Yan, Huixian Lai
-
Publication number: 20230282249Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yifei Yan, Huixian Lai
-
Publication number: 20230232620Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Huixian LAi, Chao-Wei Lin, Chia-Yi Chu
-
Patent number: 11688433Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.Type: GrantFiled: July 28, 2021Date of Patent: June 27, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yifei Yan, Huixian Lai
-
Patent number: 11641736Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.Type: GrantFiled: January 19, 2021Date of Patent: May 2, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Huixian Lai, Chao-Wei Lin, Chia-Yi Chu
-
Publication number: 20220415367Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.Type: ApplicationFiled: July 28, 2021Publication date: December 29, 2022Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yifei Yan, Huixian LAI
-
Publication number: 20220384431Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.Type: ApplicationFiled: July 29, 2021Publication date: December 1, 2022Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wang Jhan, Fu-Che Lee, Huixian LAI, Yu-Cheng Tung, An-Chi Liu, Gang-Yi Lin
-
Publication number: 20220254785Abstract: Provided are an electrical contact structure. Through enabling at least the first contact plug closest to a peripheral area to be formed above an isolation structure of a boundary area between a core area and the peripheral area and in contact with the isolation structure, and enabling a bottom portion of the first contact plug to be completely overlapped on the isolation structure, or, enabling a part of the bottom portion to be overlapped with the isolation structure, enabling the other part of the bottom portion to be overlapped with an active area (AA) of the core area next to the isolation structure, and even enabling a top portion of the first contact plug to be at least connected with a top portion of the contact plug above the AA of the core area next to the isolation structure.Type: ApplicationFiled: March 17, 2020Publication date: August 11, 2022Inventors: Huixian LAI, Yu-Cheng TUNG, Chao-Wei LIN, Chia-Yi CHU, Chien-Hung LU
-
Publication number: 20220122984Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.Type: ApplicationFiled: August 9, 2021Publication date: April 21, 2022Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Cheng Tung, Huixian LAI, Yi-Wang Jhan
-
Publication number: 20220028867Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.Type: ApplicationFiled: March 17, 2020Publication date: January 27, 2022Inventors: Chung-Yen CHOU, Chih-Yuan CHEN, Qinfu ZHANG, Chao-Wei LIN, Chia-Yi CHU, Jen-Chieh CHENG, Jen-Kuo WU, Huixian LAI
-
Publication number: 20210313422Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.Type: ApplicationFiled: June 16, 2021Publication date: October 7, 2021Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu
-
Publication number: 20210225851Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.Type: ApplicationFiled: January 19, 2021Publication date: July 22, 2021Inventors: Huixian LAI, Chao-Wei Lin, Chia-Yi Chu
-
Patent number: 11069774Abstract: A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.Type: GrantFiled: November 26, 2019Date of Patent: July 20, 2021Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu
-
Publication number: 20210098571Abstract: A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.Type: ApplicationFiled: November 26, 2019Publication date: April 1, 2021Inventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu