Patents by Inventor Huiying HOU

Huiying HOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Host controller of high-speed data interface with clock-domain crossing
    Patent number: 10042810
    Abstract: A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of the low-speed data to high-speed data and transmit the high-speed data to the corresponding external devices, and further has a multiplexer. Each EPHY corresponds to one clock signal and operates accordingly. The multiplexer receives the clock signals of the EPHYs to output a common clock signal for the LPHY to provide the groups of low-speed data and for the TXCDC to retrieve the groups of low-speed data. With respect to each of the external devices, the TXCDC uses the clock signal corresponding to the corresponding EPHY to output the corresponding group of low-speed data to the corresponding EPHY.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 7, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Wanfeng Wang, Xiaoliang Ji, Zhiqiang Hui, Huiying Hou
  • HOST CONTROLLER OF HIGH-SPEED DATA INTERFACE
    Publication number: 20170161228
    Abstract: A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of the low-speed data to high-speed data and transmit the high-speed data to the corresponding external devices, and further has a multiplexer. Each EPHY corresponds to one clock signal and operates accordingly. The multiplexer receives the clock signals of the EPHYs to output a common clock signal for the LPHY to provide the groups of low-speed data and for the TXCDC to retrieve the groups of low-speed data. With respect to each of the external devices, the TXCDC uses the clock signal corresponding to the corresponding EPHY to output the corresponding group of low-speed data to the corresponding EPHY.
    Type: Application
    Filed: June 2, 2016
    Publication date: June 8, 2017
    Inventors: Wanfeng WANG, Xiaoliang JI, Zhiqiang HUI, Huiying HOU