Patents by Inventor Huiyuan Xing

Huiyuan Xing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250028644
    Abstract: The present disclosure relates to a computer implemented method for verification of a cache memory of a device under test. The method comprises executing a cache verification process configured for accessing via an interface and verifying the cache memory of the device under test. Cache accesses to the cache memory of the device under test by the cache verification process via the interface are monitored. A cache access by the cache verification process via the interface is detected. In response to the detecting of the cache access a target of the detected cache access is determined and the cache memory is modified for providing a pre-defined cache read-out result for the detected cache access. Via the interface the pre-defined cache read-out result is returned to the cache verification process in response to the detected cache access.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 23, 2025
    Inventors: Yvo Thomas Bernard Mulder, Huiyuan Xing, Gerrit Koch, Ulrike Letz
  • Patent number: 11860789
    Abstract: A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: January 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yvo Thomas Bernard Mulder, Ralf Ludewig, Huiyuan Xing, Ulrich Mayer
  • Publication number: 20230297509
    Abstract: A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: Yvo Thomas Bernard Mulder, Ralf Ludewig, Huiyuan Xing, Ulrich Mayer