Patents by Inventor Humayun Kabir

Humayun Kabir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923424
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 5, 2024
    Assignee: NXP B.V.
    Inventors: Ibrahim Khalil, Bernhard Grote, Humayun Kabir, Bruce McRae Green
  • Publication number: 20230411243
    Abstract: A transistor die includes input and output terminals and a source through-substrate via (TSV) between the input and output terminals. First and second primary drain contacts extend from the output terminal toward the input terminal past first and second sides, respectively, of the source TSV. An ancillary region is located adjacent to the source TSV, and boundaries of the ancillary region are defined by the source TSV, the first and second drain contacts, and one of the input terminal or the output terminal. The transistor further includes a primary transistor element, including a primary drain contact, a primary source contact, and a primary gate structure, located outside of the first ancillary region, and an ancillary transistor element, including an ancillary drain contact, an ancillary source contact, and an ancillary gate structure, located within the ancillary region.
    Type: Application
    Filed: June 20, 2022
    Publication date: December 21, 2023
    Inventors: Humayun Kabir, Ibrahim Khalil, Bruce McRae Green
  • Publication number: 20230369205
    Abstract: A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Humayun Kabir, Ibrahim Khalil, Daniel Joseph Lamey, Yu-Ting David Wu
  • Patent number: 11804527
    Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: October 31, 2023
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Daniel Joseph Lamey, Bruce McRae Green, Ibrahim Khalil, Humayun Kabir
  • Publication number: 20230260935
    Abstract: A device includes a semiconductor substrate, a source metallization over an active area of the semiconductor substrate, a through-substrate via electrically connected to the source metallization, and an input bond pad formed in the semiconductor substrate and spaced apart from the active area. The input bond pad is electrically connected to a set of gate structures. The device includes a first inductive coil over the semiconductor substrate between a first portion of the source metallization and a second portion of the source metallization and a first capacitor over the semiconductor substrate between the first portion of the source metallization and the second portion of the source metallization. The first inductive coil and the first capacitor are connected in series between the input bond pad and the through-substrate via.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventors: Humayun KABIR, Vikas SHILIMKAR, Ibrahim KHALIL, Kevin KIM
  • Publication number: 20230207675
    Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, a second dielectric layer disposed over the first dielectric layer, a third dielectric layer disposed over the second dielectric layer, a lower opening formed in the first dielectric layer, an upper opening formed in the second dielectric layer and the third dielectric layer, wherein at least a portion of the upper opening overlaps a portion of the lower opening, and a control electrode formed within at least a portion of the lower opening and within a portion of the upper opening, wherein a portion of the control electrode is formed over the third dielectric layer.
    Type: Application
    Filed: December 24, 2021
    Publication date: June 29, 2023
    Inventors: Bernhard Grote, Humayun Kabir, Bruce McRae Green, Ibrahim Khalil
  • Publication number: 20230197795
    Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Inventors: Bernhard Grote, Philippe Renaud, Humayun Kabir, Bruce McRae Green, Ibrahim Khalil
  • Patent number: 11585776
    Abstract: Methods, electrodes, and sensors for chlorine species sensing using pseudo-graphite are disclosed. In one illustrative embodiment, a method may include coating a pseudo-graphite material onto a surface of an electrode substrate to produce a pseudo-graphite surface. The method may also include exposing the pseudo-graphite surface to a sample to detect chlorine species in the sample.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 21, 2023
    Assignees: ABB Schweiz AG, University of Idaho
    Inventors: Nolan Nicholas, Ignatius Cheng, Humayun Kabir, Jeremiah D. Foutch
  • Patent number: 11572176
    Abstract: A method of assessing performance of a seat is provided. The method comprises identifying a number of critical seats for testing from a layout of passenger accommodation and building a computer simulation model, following a building block approach, for each identified critical seat. A number of loads are tested on each simulation model. Critical seats are selected for physical testing from simulation model test results according to a specified criteria assessment matrix.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 7, 2023
    Assignee: The Boeing Company
    Inventors: Mohammed Humayun Kabir, Gagandeep Inder Singh Grewal, Alan Douglas Byar, Mihira Ghatuparthi, Madhava S. Kulkarni, Todd Clayton DePauw, Jan Manuelle León Gil
  • Publication number: 20230019549
    Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Inventors: Vikas Shilimkar, Kevin Kim, Daniel Joseph Lamey, Bruce McRae Green, Ibrahim Khalil, Humayun Kabir
  • Publication number: 20220376060
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor, a control electrode formed over the semiconductor substrate between the first current carrying electrode and the second current carrying electrode, and a first dielectric layer disposed over the control electrode, and a second dielectric layer disposed over the first dielectric layer. A first opening is formed in the second dielectric layer, adjacent the control electrode and the second current-carrying electrode, having a first edge laterally adjacent to and nearer the second current-carrying electrode, and a second edge laterally adjacent to and nearer to the control electrode, and a conductive element formed over the first dielectric layer and within the first opening, wherein the portion of the conductive element formed within the first opening forms a first metal-insulator-semiconductor region within the first opening.
    Type: Application
    Filed: May 20, 2021
    Publication date: November 24, 2022
    Inventors: Bernhard Grote, Humayun Kabir, Ibrahim Khalil, Bruce McRae Green
  • Patent number: 11430743
    Abstract: A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 30, 2022
    Assignee: NXP USA, Inc.
    Inventors: Humayun Kabir, Michele Lynn Miera, Charles John Lessard, Ibrahim Khalil
  • Patent number: 11430874
    Abstract: A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 30, 2022
    Assignee: NXP USA, Inc.
    Inventors: Humayun Kabir, Ibrahim Khalil
  • Patent number: 11415540
    Abstract: Methods, electrodes, and electrochemical devices using nitrogen-doped pseudo-graphite are disclosed. In one illustrative embodiment, a method may include doping a pseudo-graphite material with nitrogen to form a doped pseudo-graphite material. The method may also include applying the doped pseudo-graphite material to a surface of a substrate of an electrode.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 16, 2022
    Assignees: ABB Schweiz AG, University of Idaho
    Inventors: Nolan Nicholas, Ignatius Cheng, Haoyu Zhu, Humayun Kabir, Kailash Hamal, Jeremy May
  • Patent number: 11415539
    Abstract: Methods, electrodes, and sensors for pH sensing using pseudo-graphite are disclosed. In one illustrative embodiment, a method may include coating a pseudo-graphite material onto a surface of an electrode substrate to produce a pseudo-graphite surface. The method may also include exposing the pseudo-graphite surface to a sample to detect organic content in the sample.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 16, 2022
    Assignees: ABB Schweiz AG, University of Idaho
    Inventors: Nolan Nicholas, Ignatius Cheng, Haoyu Zhu, Humayun Kabir
  • Patent number: 11387169
    Abstract: A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: July 12, 2022
    Assignee: NXP USA, Inc.
    Inventors: Ibrahim Khalil, Kevin Kim, Humayun Kabir
  • Publication number: 20220208975
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Ibrahim Khalil, Bernhard Grote, Humayun Kabir, Bruce McRae Green
  • Publication number: 20220190126
    Abstract: A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Humayun Kabir, Ibrahim Khalil
  • Publication number: 20220044986
    Abstract: A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Ibrahim Khalil, Kevin Kim, Humayun Kabir
  • Publication number: 20220013451
    Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Vikas Shilimkar, Kevin Kim, Charles John Lessard, Humayun Kabir