Abstract: The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop (“PLL”) circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period.

Abstract: A data processing system has a memory bus and a system input/output (I/O) bus including I/O drivers. The memory and I/O buses are controlled by a central processor unit (CPU) for transferring data therebetween and to the I/O drivers. A central clock provides clock signals to the CPU, the memory bus and the I/O bus. The central clock further provides memory and I/O phase alignment signals to the CPU, the alignment signals indicating to the CPU when the start of the CPU clock cycle coincides with the start of a memory bus clock cycle or I/O bus clock signal. Circuit means responsive to the phase alignment and CPU clock signals initiate the transfer of data to the memory and I/O data buses in alternate CPU clock signals to reduce the number of I/O pin switching at any given time thereby reducing the noise and power consumption at the I/O pins and in the system.

Abstract: A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Abstract: A computer system is provided with microprocessor clocking control by providing a clock having output timing signals which vary based on input signals to the clock, setting timing parameters for the clock using a service processor which sends the input signals to the clock, and controlling the primary processor using the output timing signals from the clock. The service processor can be used to modify a pulse width of at least one of the output timing signals, and to delaying a first one of the output timing signals with respect to a second one of the output timing signals. Separate clock signals can be provided for the primary processor and other system components, such as a cache connected to the primary processor, a memory device of the computer system, or an input/output device of the computer system. The clock has a programmable duty-cycle control circuit. The duty-cycle control circuit may use delay chains having a plurality of individually selectable delay elements.

Abstract: During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.