Abstract: An implement including a first frame member, a second frame member movable with respect to the first frame member, and a rolling basket rotatably coupled to the second frame member for rotation about a first axis of rotation. The implement also includes a biasing member configured to move the first axis of rotation toward a rest position, and where the rest position is adjustable relative to the first frame portion.

Abstract: An implement including a first frame member, a second frame member movable with respect to the first frame member, and a rolling basket rotatably coupled to the second frame member for rotation about a first axis of rotation. The implement also includes a biasing member configured to move the first axis of rotation toward a rest position, and where the rest position is adjustable relative to the first frame portion.

Abstract: A harrow attachment for a tillage implement includes a harrow drawbar mounting at least one rank of harrowing tools. A pivot link pivotally couples the harrow rank to the drawbar so it can trip by pivoting upward toward the drawbar from a home position in which the harrow rank is farthest away from the drawbar. A downforce spring is coupled to the drawbar and in a variable length state when the harrow rank is tripped to apply a return biasing force to the harrow rank. An adjustment mechanism couples the spring to the harrow rank and/or the pivot link in one of a plurality of adjustment locations in each of which the harrow rank is in the home position and the spring is in a fixed length state in which the biasing force is removed.

Abstract: A harrow attachment for a tillage implement has a harrow drawbar, configured to mount to a frame member of the tillage implement, and at least one harrow rank having a rank bar supporting a plurality of harrowing tools oriented to extend away from the rank bar. An anti-tangle bracket assembly has a first pivot link coupled to the harrow drawbar and a second pivot link pivotally coupled to the at least one harrow rank. The first and second pivot links pivot about pivot axes with respect to one another within a pivotal range of movement of the at least one harrow rank from a first, extended position to a second, tripped position.

Abstract: A drawbar for finishing attachments is arranged to attach to a fore-aft frame member of a tillage implement. The drawbar has a saddle with spaced apart side walls defining a channel configured to receive the frame member. When the frame member is received in the channel, the side walls of the saddle overlap side walls of the frame member and extend in the fore-aft direction rearward of an end of the frame member. The side walls of the saddle and the frame member have mounting openings that align along a lateral direction transverse to the fore-aft direction.

Abstract: A finishing attachment for a tillage implement has a support arm configured to mount to the frame so that a long dimension of the support arm extends in a fore-aft direction of the implement. A cross-bar having a long dimension extending transverse to the fore-aft direction is coupled to a free end of the support arm. A roller basket is mounted to the cross-bar for rotation with respect to the cross-bar. A pivot bracket couples the free end of the support arm to the cross-bar. The pivot bracket forms a pivot axis extending substantially in the fore-aft direction of travel about which the roller basket pivots.

Abstract: A finishing attachment for a tillage implement has a support arm configured to mount to the frame so that a long dimension of the support arm extends in a fore-aft direction of the implement. A cross-bar having a long dimension extending transverse to the fore-aft direction is coupled to a free end of the support arm. A roller basket is mounted to the cross-bar for rotation with respect to the cross-bar. A pivot bracket couples the free end of the support arm to the cross-bar. The pivot bracket forms a pivot axis extending substantially in the fore-aft direction of travel about which the roller basket pivots.

Abstract: A harrow attachment for a tillage implement has a harrow drawbar, configured to mount to a frame member of the tillage implement, and at least one harrow rank having a rank bar supporting a plurality of harrowing tools oriented to extend away from the rank bar. An anti-tangle bracket assembly has a first pivot link coupled to the harrow drawbar and a second pivot link pivotally coupled to the at least one harrow rank. The first and second pivot links pivot about pivot axes with respect to one another within a pivotal range of movement of the at least one harrow rank from a first, extended position to a second, tripped position.

Abstract: A harrow attachment for a tillage implement includes a harrow drawbar mounting at least one rank of harrowing tools. A pivot link pivotally couples the harrow rank to the drawbar so it can trip by pivoting upward toward the drawbar from a home position in which the harrow rank is farthest away from the drawbar. A downforce spring is coupled to the drawbar and in a variable length state when the harrow rank is tripped to apply a return biasing force to the harrow rank. An adjustment mechanism couples the spring to the harrow rank and/or the pivot link in one of a plurality of adjustment locations in each of which the harrow rank is in the home position and the spring is in a fixed length state in which the biasing force is removed.

Abstract: A drawbar for finishing attachments is arranged to attach to a fore-aft frame member of a tillage implement. The drawbar has a saddle with spaced apart side walls defining a channel configured to receive the frame member. When the frame member is received in the channel, the side walls of the saddle overlap side walls of the frame member and extend in the fore-aft direction rearward of an end of the frame member. The side walls of the saddle and the frame member have mounting openings that align along a lateral direction transverse to the fore-aft direction.

Abstract: A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register.

Abstract: A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register.

Abstract: Object-code compatibility is provided among VLIW processors with different organizations. The object-code can also be executed by sequential processors, thus providing compatibility with scalar and superscalar processors, A mechanism is provided which allows representing VLIW programs in an implementation-independent manner. This mechanism relies on instruction cache (I-cache) reload/access logic which incorporates implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation-independent manner, the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved. The foregoing allows for object-code compatibility among VLIW processors with different organizations. Also provided is a mechanism and an apparatus for the interpretation of tree-instructions by a computer system based on a VLIW processor.

Abstract: The present invention is an apparatus that maps the memory address space of the computer system into regions, and detects the incorrect execution of a load operation performed earlier than a sequentially preceding (in program order) store operation. The apparatus detects out-of-order load operations, uses a region-based mapping table to keep track of the memory regions accessed by the out-of-order load operations, detects the execution of store operations into regions accessed by out-of-order load operations, and generates a program exception when interference among reordered operations is detected. The invention is applicable to static and dynamic reordering of memory operations.

Abstract: In a computer system having a hierarchical memory, the problem of tolerating cache miss latency is solved by dynamically switching appropriately between two different code sequences, one optimized at compile-time, assuming a cache-hit, and the other optimized at compile-time, assuming a cache-miss.

Abstract: A computer processing system stores sequences of instructions in a memory for execution by a processor unit. An out-of-order load instruction may be created, either statically or dynamically, by moving a load instruction from its original position in a sequence of instructions to an earlier position in said sequence of instructions. Such out-of-order load instruction identifies a location in memory from which to read a datum and a first destination register in which to place the datum. The present invention is a method and corresponding apparatus that utilizes data comparison to detect coherence among memory and the datum read by an out-of-order load operation. More specifically, the method consists of an interference test which controls the processor unit to read a datum from the same location in memory identified by the out-of-order load instruction and compare the newly read datum with the datum saved in the first destination register.

Abstract: Object code compatibility is provided among VLIW processors with different organizations. The object code can be executed by sequential processors, thus providing backward compatibility with scalar and superscalar processors. A mechanism is provided which allows representing VLIW programs in an implementation independent manner. This mechanism relies on instruction cache (I-cache) reload/access processes which incorporate implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation independent manner (i.e., without reflecting the organization of the processor where they are executed), the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved. This allows for object code compatibility among VLIW processors with different organizations.