Abstract: A yaw control-by-rudder type tidal stream power generation apparatus includes: a nacelle used in a tidal stream power generator that converts flowing energy of a tidal stream to generate electric power, and located in the tidal stream to be rotatable about a first rotating shaft; a rotor provided at one side of the nacelle with reference to the first rotating shaft, and configured to be rotated by the flowing energy of the tidal stream; a rudder unit provided at the other side of the nacelle with reference to the first rotating shaft, and including a rudder fixed to the nacelle and a variable rudder rotatably connected to the nacelle; and a control unit configured to control the rotation of the variable rudder. When the flow direction of the tidal stream is changed, the rotation of the variable rudder is controlled by the control unit.

Abstract: A yaw control-by-rudder type tidal stream power generation apparatus includes: a nacelle used in a tidal stream power generator that converts flowing energy of a tidal stream to generate electric power, and located in the tidal stream to be rotatable about a first rotating shaft; a rotor provided at one side of the nacelle with reference to the first rotating shaft, and configured to be rotated by the flowing energy of the tidal stream; a rudder unit provided at the other side of the nacelle with reference to the first rotating shaft, and including a rudder fixed to the nacelle and a variable rudder rotatably connected to the nacelle; and a control unit configured to control the rotation of the variable rudder. When the flow direction of the tidal stream is changed, the rotation of the variable rudder is controlled by the control unit.

Abstract: A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.

Abstract: A field emission panel, and a liquid crystal display and a field emission display using the same are provided. The field emission panel includes an upper plate including a first glass plate and a phosphor layer formed on the first glass plate; a lower plate including a second glass plate disposed parallel to the first glass plate and a plurality of electron emission elements provided on the second glass plate; a plurality of spacers disposed between the upper plate and the lower plate; a third glass plate disposed on a rear of the lower plate to form a getter room; and at least one post disposed in the getter room to support the lower plate and the third glass plate.

Abstract: A Plasma Display Panel (PDP) includes: a first substrate and a second substrate that are arranged in parallel with each other with a predetermined distance therebetween; a plurality of address electrodes arranged on the first substrate; a first dielectric layer arranged to cover the address electrodes; a plurality of barrier ribs having a predetermined height from the first dielectric layer to define discharge cells; red, blue, and green phosphor layers respectively arranged in the discharge cells; a plurality of display electrodes arranged on one side of the second substrate facing the first substrate in a direction crossing the address electrodes; a second dielectric layer arranged to cover the display electrodes; and a protective layer arranged to cover the second dielectric layer. The second dielectric layer satisfies values of CIE L*a*b* where 70.0<L*<74.5, 0.0<a*<1.0, and ?5.0<b*<?8.0.

Abstract: A plasma display panel having a uniformly distributed firing voltage despite of irregular discharge gaps, the plasma display panel including a first substrate, a second substrate facing the first substrate, barrier ribs between the first and second substrates to define discharge cells, address electrodes corresponding to the discharge cells and extending in a first direction, first and second electrodes respectively extending in a second direction crossing the first direction and formed on any one of the first and second substrates, corresponding to the discharge cells, and a dielectric layer covering the first and second electrodes, where the first and second electrodes are spaced apart from each other to form a discharge gap having distances, the dielectric layer having varied permittivities according to distances of the discharge gaps to improve discharge uniformity according to the distances of the discharge gaps.

Abstract: A plasma display panel, and a method of manufacturing the same, including a substrate, barrier ribs formed on the substrate and defining discharge cells and non-discharge cells, the barrier ribs including first, second and third barrier rib members, wherein the discharge cells are defined by the first and second barrier rib members, the second barrier rib members perpendicular to and intersecting the first barrier rib members, the non-discharge cells are defined by the second and third barrier rib members, wherein the third barrier rib members are located between columns of the discharge cells and are disposed parallel to the first barrier rib members, and a cross-sectional area of at least one third barrier rib member is greater at a bottom portion of the at least one third barrier rib member than at a top portion thereof.

Abstract: A plasma display panel (PDP) includes front and rear substrates spaced apart and facing each other, a plurality of display electrodes along a first direction on the front substrate, a plurality of address electrodes along a second direction on the rear substrate, the second direction crossing the first direction, a dielectric layer on the rear substrate to cover the address electrodes, barrier ribs between the front and rear substrates to define a plurality of discharge cells, a bottom surface of the barrier ribs being on the dielectric layer, and a phosphor layer on the dielectric layer, at least one portion of the phosphor layer being arranged between the dielectric layer and the bottom surface of the barrier ribs.

Abstract: A plasma display panel, and a method of manufacturing the same, including a substrate, barrier ribs formed on the substrate and defining discharge cells and non-discharge cells, the barrier ribs including first, second and third barrier rib members, wherein the discharge cells are defined by the first and second barrier rib members, the second barrier rib members perpendicular to and intersecting the first barrier rib members, the non-discharge cells are defined by the second and third barrier rib members, wherein the third barrier rib members are located between columns of the discharge cells and are disposed parallel to the first barrier rib members, and a cross-sectional area of at least one third barrier rib member is greater at a bottom portion of the at least one third barrier rib member than at a top portion thereof.

Abstract: Provided is a plasma display panel including: a first substrate and a second substrate facing each other; an upper dielectric layer formed on the inner surface of the first substrate; and a first ceramic layer which has about the same thermal expansion coefficient as the upper dielectric layer, faces the upper dielectric layer, and is formed on the outer surface of the first substrate. Alternatively, the plasma display panel includes: a first lower dielectric layer formed on the second substrate and having a thermal expansion coefficient greater than that of the second substrate by ?; and a second lower dielectric layer formed on the first lower dielectric layer and having a thermal expansion coefficient less than that of the second substrate by ?.

Abstract: A plasma display device including: a plasma display panel adapted to create images and including a front substrate, a rear substrate, a plurality of discharge cells defined between the front substrate and the rear substrate, and phosphors coated in the discharge cells; and a filter attached to a front surface of the front substrate and adapted to serve as an image display surface, wherein the filter and the phosphors are respectively colored with first and second colors that are different from each other.

Abstract: A Plasma Display Panel (PDP) includes: a first substrate and a second substrate that are arranged in parallel with each other with a predetermined distance therebetween; a plurality of address electrodes arranged on the first substrate; a first dielectric layer arranged to cover the address electrodes; a plurality of barrier ribs having a predetermined height from the first dielectric layer to define discharge cells; red, blue, and green phosphor layers respectively arranged in the discharge cells; a plurality of display electrodes arranged on one side of the second substrate facing the first substrate in a direction crossing the address electrodes; a second dielectric layer arranged to cover the display electrodes; and a protective layer arranged to cover the second dielectric layer. The second dielectric layer satisfies values of CIE L*a*b* where 70.0<L*<74.5, 0.0<a*<1.0, and ?5.0<b*<?8.0.

Abstract: A plasma display panel having a uniformly distributed firing voltage despite of irregular discharge gaps, the plasma display panel including a first substrate, a second substrate facing the first substrate, barrier ribs between the first and second substrates to define discharge cells, address electrodes corresponding to the discharge cells and extending in a first direction, first and second electrodes respectively extending in a second direction crossing the first direction and formed on any one of the first and second substrates, corresponding to the discharge cells, and a dielectric layer covering the first and second electrodes, where the first and second electrodes are spaced apart from each other to form a discharge gap having distances, the dielectric layer having varied permittivities according to distances of the discharge gaps to improve discharge uniformity according to the distances of the discharge gaps.

Abstract: A plasma display panel capable of stabilizing a discharge characteristic by integrating discharge cells with a high density and efficiently exhausting the plasma display panel is provided. The plasma display panel is constructed with: first and second substrates facing each other; barrier ribs disposed between the first and second substrates to define discharge cells; address electrodes extending in a first direction and corresponding to the discharge cells; and first and second electrodes extending in a second direction that crosses the first direction and corresponding to the discharge cells. The red, green, and blue discharge cells among the discharge cells are disposed in a triangular shape. Exhaust paths are formed between neighboring discharge cells.

Abstract: A plasma display panel, and a method of manufacturing the same, including a substrate, barrier ribs formed on the substrate and defining discharge cells and non-discharge cells, the barrier ribs including first, second and third barrier rib members, wherein the discharge cells are defined by the first and second barrier rib members, the second barrier rib members perpendicular to and intersecting the first barrier rib members, the non-discharge cells are defined by the second and third barrier rib members, wherein the third barrier rib members are located between columns of the discharge cells and are disposed parallel to the first barrier rib members, and a cross-sectional area of at least one third barrier rib member is greater at a bottom portion of the at least one third barrier rib member than at a top portion thereof.

Abstract: Disclosed is a system for fabricating a liquid crystal display using liquid crystal dropping and a method of fabricating a liquid crystal display using the same. The present invention includes a liquid crystal forming line dropping liquid crystals on the first substrate, a sealant forming line forming the sealant on the second substrate, and a bonding and hardening line bonding the two substrates to each other and hardening the sealant, printing a sealant, bonding the substrates each other, and hardening the sealant and an inspection process line of cutting the bonded substrates into panel units and grinding and inspecting the unit panels.

Abstract: Disclosed is a system for fabricating a liquid crystal display using liquid crystal dropping and a method of fabricating a liquid crystal display using the same. The present invention includes a liquid crystal forming line dropping liquid crystals on the first substrate, a sealant forming line forming the sealant on the second substrate, and a bonding and hardening line bonding the two substrates to each other and hardening the sealant, printing a sealant, bonding the substrates each other, and hardening the sealant and an inspection process line of cutting the bonded substrates into panel units and grinding and inspecting the unit panels.

Abstract: A cassette facilitates the inspection of liquid crystal panels and prevents breakage of the liquid crystal panels. The cassette includes a frame, plates arranged substantially parallel at top and bottom portions of the frame, and slots secured to the plates so as to secure the liquid crystal panels arranged within the cassette.

Abstract: An electron gun includes a cathode, a control electrode, a screen electrode arranged in front of the control electrode, at least one focusing electrode arranged in front of the screen electrode to form a pre-focusing lens unit, a final accelerating electrode arranged in front of the focusing electrode(s) to form a main lens unit, and a shield cup electrically connected to the final accelerating electrode. The iron-chromium-nickel alloy for the focusing electrode(s), the final accelerating electrode, and the shield cup contains 18-20% or less by weight of chromium, 8-10% by weight of nickel, 0.03% or less by weight of carbon, 1.00% by weight of silicon, 2.00% or less by weight of manganese, 0.04% or less by weight of phosphorous, 0.03% or less by weight of sulfur, a balance of iron, and a trace of impurities, and has an average granularity of 0.010-0.022 mm.