Abstract: A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.

Abstract: A system-on-chip includes a substrate, a plurality of unit cells on the substrate, a first power mesh, and a second power mesh. The first power mesh includes a power rail that is connected to power terminals of the plurality of unit cells and is provided in a first metallization layer. The first power mesh also includes a power strap in a second metallization layer. The second power mesh is provided in a third metallization layer and a fourth metallization layer.

Abstract: Exemplary embodiments provide a UV light emitting diode and a method of fabricating the same. The method of fabricating a UV light emitting diode includes growing a first n-type semiconductor layer including AlGaN, wherein growth of the first n-type semiconductor layer includes changing a growth pressure within a growth chamber and changing a flow rate of an n-type dopant source introduced into the growth chamber. A pressure change during growth of the first n-type semiconductor layer includes at least one cycle of a pressure increasing period and a pressure decreasing period over time, and change in flow rate of the n-type dopant source includes increasing the flow rate of the n-type dopant source in the form of at least one pulse. The UV light emitting diode fabricated by the method has excellent crystallinity.

Abstract: A semiconductor integrated circuit comprising: a first macro cell including a first power line in a first wiring layer; a second macro cell adjacent to the first macro cell, the second macro cell including a second power line in the first wiring layer; a first connection part in the first wiring layer, the first connection part electrically connecting the first power line with the second power line; and a third power line in a second wiring layer different from the first wiring layer, the third power line electrically connected to the first power line; wherein the second power line is electrically connected to the third power line through the first connection part.

Abstract: A charge pump provides an output voltage with reduced voltage ripple. The charge pump includes a first capacitor, a second capacitor, and a control circuit. The control circuit charges the first capacitor to one of a first voltage and a second voltage and the second capacitor to the other one of the first and second voltages using differential clock signals and an input voltage during each clock phase and outputs the higher one of the first and second voltages as an output voltage.

Abstract: A UV light emitting diode and a method of fabricating the same are provided. The light emitting diode includes an active area between an n-type nitride-based semiconductor layer and a p-type nitride-based semiconductor layer, wherein the active area includes a plurality of barrier layers containing Al, a plurality of well layers containing Al and alternately arranged with the barrier layer, and at least one conditioning layer. Each conditioning layer is placed between the well layer and the barrier layer adjacent to the well layer and is formed of a binary nitride semiconductor. The design of the conditioning layer can reduce stress of the active area while allowing uniform control of the composition of the well layers and/or the barrier layers.

Abstract: A method of fabricating a semiconductor device includes forming an insulation pattern including a mask region and an open region on a gallium nitride substrate, growing gallium nitride semiconductor layers to cover the insulation pattern, and patterning the semiconductor layers to form a plurality of semiconductor stacks separated from each other, the plurality of semiconductor stacks being electrically isolated from the gallium nitride substrate by the insulation pattern.

Abstract: Embodiments of the disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate.

Abstract: Exemplary embodiments provide a UV light emitting diode and a method of fabricating the same. The method of fabricating a UV light emitting diode includes growing a first n-type semiconductor layer including AlGaN, wherein growth of the first n-type semiconductor layer includes changing a growth pressure within a growth chamber and changing a flow rate of an n-type dopant source introduced into the growth chamber. A pressure change during growth of the first n-type semiconductor layer includes at least one cycle of a pressure increasing period and a pressure decreasing period over time, and change in flow rate of the n-type dopant source includes increasing the flow rate of the n-type dopant source in the form of at least one pulse. The UV light emitting diode fabricated by the method has excellent crystallinity.

Abstract: Provided is a power management device which includes a first regulator, a second regulator and a control register unit. The first regulator provides a first driving voltage to a first power domain of an application processor. The second regulator provides a second power domain of the application processor with a second driving voltage having a correlation with the first driving voltage. The control register unit controls, in response to a command from the application processor, a reference voltage generation circuit that provides a first reference voltage and a second reference voltage to the first regulator and the second regulator, respectively. The level of the first driving voltage is maintained in a first driving mode. The first driving voltage and the second driving voltage have a set voltage difference in a second driving mode.

Abstract: Disclosed are a method for separating a growth substrate, a method for manufacturing a light-emitting diode, and the light-emitting diode. The method for separating a growth substrate, according to one embodiment, comprises: preparing a growth substrate; forming a sacrificial layer and a mask pattern on the growth substrate; etching the sacrificial layer by using electrochemical etching (ECE); covering the mask pattern, and forming a plurality of nitride semiconductor stacking structures which are separated from each other by an element separation area; attaching a support substrate to the plurality of semiconductor stacking structures, wherein the support substrate has a plurality of through-holes connected to the element separation area; and separating the growth substrate from the nitride semiconductor stacking structures.

Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.

Abstract: Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.

Abstract: A power path controller included in a system-on-chip (SoC) is provided. The power path controller is coupled to a first power source and a second power source. The power path controller includes a first switch located between the first power source and a memory core included in the SoC, a second switch located between the second power source and the memory core, a comparator configured to compare a first power supply voltage supplied from the first power source with a second power supply voltage supplied from the second power source, and a switch controller configured to selectively activate the first switch or the second switch according to a comparison result of the comparator.

Abstract: The present invention relates to a technique for manufacturing a unit cell for a solid oxide fuel cell (SOFC) which can improve the output of the unit cell of the solid oxide fuel cell, without occurring cost due to an additional process. The unit cell of the solid oxide fuel cell, comprises: a fuel electrode support body; a fuel electrode reaction layer; an electrolyte; and an air electrode, wherein the fuel electrode support body is made from an NiO and YSZ mixed material, the fuel electrode reaction layer is made from a CeScSZ and NiO mixed material, the electrolyte is made from a CeCsSZ material, and wherein the air electrode is made from an LSM and CeScSZ mixed material.

Abstract: In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.

Abstract: A method of controlling a load current is provided. By the method, a battery voltage control operation is begun when a battery voltage becomes lower than a first threshold value, whether a gradient of the battery voltage is a positive gradient or a negative gradient is determined at an interval of a reference or, alternatively, predetermined control time, the load current is controlled based on the gradient of the battery voltage at an interval of the reference or, alternatively, predetermined control time, and the battery voltage control operation is finished when the battery voltage becomes higher than a second threshold value.

Abstract: An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals.

Abstract: A system-on-chip includes a substrate, a plurality of unit cells on the substrate, a first power mesh, and a second power mesh. The first power mesh includes a power rail that is connected to power terminals of the plurality of unit cells and is provided in a first metallization layer. The first power mesh also includes a power strap in a second metallization layer. The second power mesh is provided in a third metallization layer and a fourth metallization layer.

Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.