Abstract: A process for forming a W-poly gate stack (110) comprising the steps of: (1) deposition of doped polysilicon (112) on a thin dielectric layer (108) covered substrate (102), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (114) and to remove excess nitrogen and (4) deposition of W layer (116). The stack layers are then etched to form the gate electrode (110).

Abstract: A capacitor, and a method for making the same, are disclosed, wherein one plate of the capacitor comprises silicon. The dielectric material of the capacitor includes a silicon nitride layer disposed adjacent the silicon plate, and a layer of yttrium oxide disposed thereover. The second plate of the capacitor is formed over the yttrium oxide layer. The silicon nitride provides a barrier to the diffusion of silicon into the yttrium oxide film if the structure is heated, providing for a high dielectric constant capacitor dielectric which has improved leakage characteristics.