Abstract: A mote includes an optical receiver that wirelessly receives a power and data signal in form of NIR light energy within a patient and converts the NIR light energy to an electrical signal having a supply voltage. A control module supplies the supply voltage to power devices of the mote. A clock generation circuit locks onto a target clock frequency based on the power and data signal and generates clock signals. A data recovery circuit sets parameters of one of the devices based on the power and data signal and a first clock signal. An amplifier amplifies a neuron signal detected via an electrode inserted in tissue of the patient. A chip identifier module, based on a second clock signal, generates a recorded data signal based on a mote chip identifier and the neuron signal. A driver transmits the recorded data signal via a LED or a RF transmitter.

Abstract: Recent advances in model pruning have enabled sparsity-aware deep neural network accelerators that improve the energy efficiency and performance of inference tasks. SONA, a novel transform-domain neural network accelerator is introduced in which convolution operations are replaced by element-wise multiplications and weights are orthogonally structured to be sparse. SONA employs an output stationary dataflow coupled with an energy-efficient memory organization to reduce the overhead of sparse-orthogonal transform-domain kernels that are concurrently processed while maintaining full multiply-and-accumulate (MAC) array utilization without any conflicts. Weights in SONA are non-uniformly quantized with bit-sparse canonical-signed-digit (BS-CSD) representations to reduce multiplications to simpler additions.

Abstract: A computer-implemented method is presented for performing a computation with a neural network. The method includes: receiving a first input patch of data; applying a Walsh-Hadamard transform to the input patch to yield a transformed input patch in a transformed domain; computing an element-wise product of the transformed input patch and a kernel of the neural network; applying an inverse Walsh-Hadamard transform to the element-wise product to yield an intermediate matrix; and creating a first output patch from the intermediate matrix, where the size of the first output patch is smaller than the intermediate matrix.

Abstract: A method of providing an augmented reality game environment within a game space includes obtaining, by a processor, sensor data for the game space, determining, by the processor, a position of a player in the game space based on the sensor data, generating, by the processor, player image data of a peripersonal boundary of the player based on the determined position of the player for rendering a representation of the peripersonal boundary in the game space, the peripersonal boundary being disposed about, and spaced from, the determined position, obtaining, by the processor, player data for the player via an input modality, the player data being indicative of a player directive to modulate the peripersonal boundary, adjusting, by the processor, a size of the peripersonal boundary as a function of the player data, and updating, by the processor, the player image data based on the adjusted size of the peripersonal boundary.

Abstract: When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

Abstract: When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

Abstract: A mote includes an optical receiver that wirelessly receives a power and data signal in form of NIR light energy within a patient and converts the NIR light energy to an electrical signal having a supply voltage. A control module supplies the supply voltage to power devices of the mote. A clock generation circuit locks onto a target clock frequency based on the power and data signal and generates clock signals. A data recovery circuit sets parameters of one of the devices based on the power and data signal and a first clock signal. An amplifier amplifies a neuron signal detected via an electrode inserted in tissue of the patient. A chip identifier module, based on a second clock signal, generates a recorded data signal based on a mote chip identifier and the neuron signal. A driver transmits the recorded data signal via a LED or a RF transmitter.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

Abstract: A method of providing an augmented reality game environment within a game space includes obtaining, by a processor, sensor data for the game space, determining, by the processor, a position of a player in the game space based on the sensor data, generating, by the processor, player image data of a peripersonal boundary of the player based on the determined position of the player for rendering a representation of the peripersonal boundary in the game space, the peripersonal boundary being disposed about, and spaced from, the determined position, obtaining, by the processor, player data for the player via an input modality, the player data being indicative of a player directive to modulate the peripersonal boundary, adjusting, by the processor, a size of the peripersonal boundary as a function of the player data, and updating, by the processor, the player image data based on the adjusted size of the peripersonal boundary.

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

Abstract: A system is presented for non-line-of-sight localization between RF enabled devices. A transmitting node is configured to transmit an RF ranging signal at a first carrier frequency, where the RF ranging signal is modulated with a symbol. The reflecting node is configured to receive the RF ranging signal and further operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal while simultaneously receiving the RF ranging signal. The localizing node is configured to receive the converted ranging signal from the reflecting node. The localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal. The transmitting node and the localizing node may be on the same or different devices.

Abstract: Methods and apparatus to determine nearfield localization using phase and received signal strength indication (RSSI) diversity are disclosed. An example method includes determining a first strength of an electric field and a second strength of a magnetic field, the electric field and the magnetic field associated with an electromagnetic signal sent from a transmitter; determining a difference between the first strength and the second strength; and determining a transmitter distance based on the difference between the first strength and the second strength.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory.

Abstract: A system is presented for non-line-of-sight localization between RF enabled devices. A transmitting node is configured to transmit an RF ranging signal at a first carrier frequency, where the RF ranging signal is modulated with a symbol. The reflecting node is configured to receive the RF ranging signal and further operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal while simultaneously receiving the RF ranging signal. The localizing node is configured to receive the converted ranging signal from the reflecting node. The localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal. The transmitting node and the localizing node may be on the same or different devices.

Abstract: An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 ?W with a sensitivity of ?72 dBm at a BER of 10?3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

Abstract: Optical flow is measured between a first image and a second image by evaluating a match quantifying parameter in respect of a set of candidate flow vectors. The set of candidate flow vectors includes one or more flow vectors selected in dependence upon one or more neighbor flow vectors associated with one or more neighboring pixels to the given pixel which have previously calculated respective match quantifying parameters indicative of closest matches for the one or more neighboring pixels. The set of candidate flow vectors also includes adjacent flow vectors corresponding to target pixels surrounding the target pixels identified by the neighbor flow vectors. One or more randomly selected random flow vectors is also added to the set of candidate flow vectors. The calculated match quantifying parameters are weighted in dependence upon whether the corresponding candidate flow vector is similar to any other candidate flow vector.

Abstract: A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit. The driver circuit is electrically coupled to the antenna and includes at least one pair of cross-coupled transistors. The bias circuit is electrically coupled to the driver circuit. In a transmit mode, the bias circuit biases the driver circuit with a first bias current. In response to the first bias current, the driver circuit oscillates the antenna. In a receive mode, the bias circuit biases the driver circuit with a second bias current, such that the first bias current differs from the second bias current. In response to the second bias current, the bias circuit amplifies a signal received by the antenna.

Abstract: An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 ?W with a sensitivity of ?72 dBm at a BER of 10?3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

Abstract: Subject matter disclosed herein may relate to arithmetic units of processors, and may relate more particularly to configurable arithmetic units. Configurable arithmetic units may comprise a plurality of basic units, and may further comprise a programmable fabric to selectively connect the plurality of basic units at least in part to process one or more sets of parameters in accordance with one or more specified arithmetic operations.

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.