Abstract: An apparatus includes a processor configured to execute instructions, and a memory storing the instructions, which when executed by the processor configure the processor to generate system error prediction data using an error prediction neural network provided with one of a plurality of log data sequences generated by pre-processing a plurality of log data pieces of component log data of a system. The system error prediction data comprises information of a plurality of system errors occurring at a plurality of respective timepoints.

Abstract: A processor-implemented method with checkpointing includes: performing an operation for learning of an artificial neural network (ANN) model; and performing a checkpointing to store information about a state of the ANN model, simultaneously with performing the operation for the learning of the ANN model.

Abstract: A stacked IC package includes a first die including a first power transmission region, an adapter die stacked on the first die, a second die stacked on the adapter die and including a second power transmission region, and a first power transmission path electrically connected between the second power transmission region and the first power transmission region through the adapter die. The first power transmission path includes a first power transmission part penetrating a portion of the adapter die in a vertical direction from the first power transmission region, a second power transmission part including a connected part in a horizontal direction from the first power transmission part in the adapter die, and a third power transmission part connected to the second power transmission region in the vertical direction from the second power transmission part. A voltage conversion circuit is arranged on the first power transmission path.

Abstract: An electronic device and method with on-demand accelerator checkpointing are provided. In one general aspect, an electronic device includes a host processor, and an accelerator configured to operate according to instructions transmitted by the host processor to the accelerator, wherein, a memory of the host processor and a memory of the accelerator are respectively checkpointed to a storage at respective different intervals, and in response to a determination that a failure has occurred in the host processor, the memory of the accelerator is checkpointed to the storage.

Abstract: An analytic structure includes a plurality of analytic fields formed on a predetermined region of a semiconductor substrate; semiconductor transistors arranged in the analytic fields to compose an array structure, each transistor having a gate electrode and an impurity region; wordlines arranged crosswise on the analytic fields and connecting the semiconductor transistors; and bitline structures connecting the impurity regions of the semiconductor transistors lengthwise, each bitline structure having a bitline and a vertical interconnection structure connecting the bitline with the impurity region. The bitlines have different heights according to their positions on the analytic fields.