Abstract: A method for estimating timing offset in an OFDM wireless communication system using preamble and pilot includes: estimating a carrier offset by using preamble included in a currently received OFDM packet and estimating a first timing offset based on the estimated carrier offset to thereby produce a first timing offset estimation value; estimating a second timing offset to thereby produce a second timing offset estimation value by transforming the OFDM packet into signals of frequency domain and using a pilot signal of the frequency-domain signals; checking a channel condition based on packet error information of a previously received packet to thereby produce error condition information, and selecting one between the first timing offset estimation value and the second timing offset estimation value based on the error condition information; and compensating data signals for timing offset among the frequency-domain signals the based on the selected timing offset estimation value.

Abstract: A transmitter/receiver for a wireless communication system is provided. The transmitter for a wireless communication system includes: an external amplifier connected to a next stage of a power amplifier amplifying a signal to be transmitted to a required power level; a transmission selector configured to directly output the signal amplified by the power amplifier to an antenna or control the external amplifier to amplify the signal, based on a mode control signal; and a mode selector configured to compare a power level of a signal provided from a receiver with a predetermined power level to generate the mode control signal for determining whether or not to operate the external amplifier.

Abstract: Provided are apparatus and method for receiving signals in a wireless communication system.

Abstract: Provided is a correlation apparatus based on symmetry of a correlation coefficient that can reduce complexity of hardware by reducing the number of adders and multipliers. Accordingly, when values of a real number part and an imaginary number part are exchanged with respect to a middle point of a correlation coefficient sequence and divided into two parts of left and right by the middle point of the correlation coefficient sequence, the values of the real number part and the imaginary number part are even-symmetrical with respect to the middle point of the divided two parts. Therefore, the number of the adders required for forming the correlation apparatus is reduced by at least 20% and the number of the multipliers is reduced by at least 70% in comparison with the 62 adders and the 64 multipliers required for a conventional correlation apparatus.

Abstract: Provided is a link adaptation method and apparatus in wireless communication system. The method, includes: amplifying a received signal; converting the amplified signal into a digital signal; calculating digital signal strength; and calculating the received signal strength based on the digital signal strength and a gain of said amplifying a received signal.

Abstract: Provided is an apparatus and method for encoding a Low Density Parity Check (LDPC) code using a message passing algorithm. The apparatus, includes: a parity calculating unit for operating a check node value on an input bit and a predetermined parity bit according to the message passing algorithm and calculating a parity bit; a parity correcting unit for correcting the calculated parity bit according to a parity check result of the calculated parity bit; and an output transform unit for combining the input bit and the corrected parity bit.

Abstract: Provided are a transmitter and receiver for a high throughput wireless communication system using a multiple antenna, a method thereof, and a digital intermediate frequency (DIF) transmission signal processing method for the same. The transmitter, includes: a baseband transmitting unit for processing a transmission signal by performing a Media Access Control (MAC) protocol process on transmission data and dividing the transmission data into n band signals where n is a predetermined natural number in a physical layer process; a DIF transmitting unit for integrating transmission signals of each band transmitted from the baseband transmitting unit and outputting m channels where m is a predetermined natural number; and a Radio Frequency (RF) transmitting unit for modulating each channel signal transmitted from the DIF transmitting unit into an RF signal and emitting the signal through the multiple antenna.

Abstract: A constellation mapping apparatus, which can reduce the storage capacity of a memory to one fourth by only storing constellation points in one quadrant of each constellation map rather than storing all the constellation points in each of the constellation maps, is provided. The constellation mapping apparatus includes a memory, an address generation block, a complementation logic block, and a scaling block. In the memory, constellation values in one of four quadrants of each constellation. The address generation block receives constellation point data, bits-per-symbol information, and valid symbol information indicating whether or not the bits-per-symbol information is valid, and generates address information of the memory where the constellation values corresponding to the constellation point data are stored and quadrant information indicating a quadrant where the constellation point data are placed.

Abstract: The present invention relates an automatic gain control device, which performs a high-speed gain control operation in high-speed data communication using burst signals, generates a gain code without using a memory or storage device to simplify a system configuration, and establishes a correct gain control operation. The automatic gain control apparatus includes a power detector for calculating a mean power of the output signal of the variable gain amplifier; a gain code generator for receiving a mean power from the power detector, and generating a gain code corresponding to the received mean power; and a voltage generator for calculating a difference between the gain code and a target gain code associated with the output signal of the variable gain amplifier to detect an error code, and generating a gain control voltage for compensating for the difference between the two gain codes on the basis of the detected error code.

Abstract: An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory unit includes a plurality of memory banks, which are capable of being independently controlled so that data can be written or read in/from the memory banks, each having memory cells arranged in an N×M matrix structure. The memory write/read control unit generates control signals to write/read data in/from the memory unit. The memory access address generation unit generates a memory access address used to write/read data in/from the memory unit in response to the memory write/read control signals. The second permutation and output selection unit rearranges the positions of data bits output from the memory unit and outputs the position-rearranged data bits.

Abstract: Provided is an apparatus and method for detecting a packet in a Wireless Local Area Network (WLAN) which can reduce a processing time of packet detection based on Orthogonal Frequency Division Multiplexing (OFDM) by detecting a received packet employing symmetry of a short preamble. The packet detecting apparatus includes an autocorrelation average power calculation unit for calculating an absolute value of an autocorrelation average power value obtained by delaying a preamble signal of a received signal by half of a preamble length, an average power calculation unit for calculating an average power value of the received signal, a power ratio calculation unit for calculating a ratio of the average power value to the absolute value of the average power value, and a packet detection unit for detecting the packet by using the power ratio calculated by the power ratio calculation unit.

Abstract: Provided is a correlation apparatus based on symmetry of a correlation coefficient that can reduce complexity of hardware by reducing the number of adders and multipliers, and a method thereof. The correlation apparatus for correlating a complex correlation coefficient sequence which is symmetrical with respect to a received complex signal sequence includes a delaying means for delaying the received complex signal sequence; a first adding means for adding the complex signal sequence delayed in the delaying means; a second adding means for adding each output signal of the first adding means; a correlation coefficient multiplying means for multiplying each output signal of the second adding means by a complex correlation coefficient of the complex correlation coefficient sequence; and a final output adding means for adding each output signal of the correlation coefficient multiplying means.

Abstract: A constellation mapping apparatus, which can reduce the storage capacity of a memory to one fourth by only storing constellation points in one quadrant of each constellation map rather than storing all the constellation points in each of the constellation maps, is provided. The constellation mapping apparatus includes a memory, an address generation block, a complementation logic block, and a scaling block. In the memory, constellation values in one of four quadrants of each constellation. The address generation block receives constellation point data, bits-per-symbol information, and valid symbol information indicating whether or not the bits-per-symbol information is valid, and generates address information of the memory where the constellation values corresponding to the constellation point data are stored and quadrant information indicating a quadrant where the constellation point data are placed.

Abstract: A constellation mapping apparatus, which can reduce the storage capacity of a memory to one fourth by only storing constellation points in one quadrant of each constellation map rather than storing all the constellation points in each of the constellation maps, is provided. The constellation mapping apparatus includes a memory, an address generation block, a complementation logic block, and a scaling block. In the memory, constellation values in one of four quadrants of each constellation. The address generation block receives constellation point data, bits-per-symbol information, and valid symbol information indicating whether or not the bits-per-symbol information is valid, and generates address information of the memory where the constellation values corresponding to the constellation point data are stored and quadrant information indicating a quadrant where the constellation point data are placed.

Abstract: A constellation mapping apparatus, which can reduce the storage capacity of a memory to one fourth by only storing constellation points in one quadrant of each constellation map rather than storing all the constellation points in each of the constellation maps, is provided. The constellation mapping apparatus includes a memory, an address generation block, a complementation logic block, and a scaling block. In the memory, constellation values in one of four quadrants of each constellation. The address generation block receives constellation point data, bits-per-symbol information, and valid symbol information indicating whether or not the bits-per-symbol information is valid, and generates address information of the memory where the constellation values corresponding to the constellation point data are stored and quadrant information indicating a quadrant where the constellation point data are placed.

Abstract: Level shifter circuit which can make an efficient level shift to level up or level down according to a change of a digital logic characteristic, including a comparator for comparing an up/down control signal to a reference signal in disabling either one of the level up shifter or the level down shifter according to the up/down control signal, a level up shifter unit for leveling up of an input voltage in response to a level up shifter/level down shifter disable signal from the comparator, a level down shifter unit for leveling down of an input voltage in response to a level up shifter/level down shifter disable signal from the comparator; and an analog multiplexer for selectively providing a leveled up signal or a leveled down signal from the level up shifter unit or the level down shifter unit.

Abstract: A clock divider of a preferred embodiment generates an output clock signal having one of even and odd number of clock cycles of an input clock signal. The output clock signal has a duty cycle of about 50%. In a preferred embodiment, the clock divider includes a divisor circuit, a control circuit and an output circuit.