Patents by Inventor Hung-Chan CHEN

Hung-Chan CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162349
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Patent number: 11944016
    Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11916146
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Publication number: 20200230513
    Abstract: A toy building block set includes a socket block piece and at least one of first and second plug block pieces. The socket block piece has a socket wall body and at least one engaging hole of a regular polygonal shape. Each of the first and second plug block pieces has a plug body and at least one polygonal insert plug configured to be inserted into and in frictional engagement with the engaging hole with a first frictional force to permit rotation of the plug block piece relative to the socket block piece by a forcible torque and to keep a predetermined angle of the plug block piece relative to the socket block piece when the forcible torque is removed. The plug body is partially inserted into and in frictional engagement with the engaging hole with a second frictional force larger than the first frictional force.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 23, 2020
    Inventors: Chia-Hao CHAO, Hung-Chan CHEN, Chih-Kai CHANG, Szu-Yuan TENG, Zhi-Hong XU