Patents by Inventor Hung-Chang Hsu
Hung-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9165838Abstract: Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.Type: GrantFiled: February 26, 2014Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Wen Nieh, Hung-Chang Hsu, Wei-Jung Lin, Yan-Ming Tsai, Chen-Ming Lee, Mei-Yun Wang
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Publication number: 20150243565Abstract: Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHUN-WEN NIEH, HUNG-CHANG HSU, WEI-JUNG LIN, YAN-MING TSAI, CHEN-MING LEE, MEI-YUN WANG
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Publication number: 20150115335Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tien-Chun WANG, Yi-Chun LO, Chia-Der CHANG, Guo-Chiang CHI, Chia-Ping LO, Fu-Kai YANG, Hung-Chang HSU, Mei-Yun WANG
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Patent number: 8536010Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.Type: GrantFiled: October 5, 2012Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wen-Chi Tsai, Mei-Yun Wang, Chii-Ming Wu, Wei-Jung Lin, Chih-Wei Chang
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Patent number: 8304319Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.Type: GrantFiled: July 14, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wen-Chi Tsai, Mei-Yun Wang, Chii-Ming Wu, Wei-Jung Lin, Chih-Wei Chang
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Publication number: 20120012903Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wen NIEH, Hung-Chang HSU, Wen-Chi TSAI, Mei-Yun WANG, Chii-Ming WU, Wei-Jung LIN, Chih-Wei CHANG
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Patent number: 6954868Abstract: A detection apparatus for use in a touch pad, for detecting the coordinates indicated by a user on the touch pad and the behavior of the user on the touch pad. The touch pad includes an X-layer and a Y-layer, and the X- and Y-layers are planar resistors. The detection apparatus has a sleep mode and an operative mode. When the user touches the touch pad, the X- and Y-layers are electrically coupled at a touch point. The detection apparatus includes a central processor, a coordinate detecting unit, an analog-to-digital converting unit, and a wake-up unit. The coordinate detecting unit is used to determine and output an X-coordinate voltage and a Y-coordinate voltage, wherein the X- and Y-coordinate voltages correspond to the touch point. The analog-to-digital converting unit is used to convert the X- and Y-coordinate voltages into an X-coordinate and a Y-coordinate, and to output the X- and Y-coordinate.Type: GrantFiled: December 31, 2001Date of Patent: October 11, 2005Assignee: Darfon Electronics Corp.Inventors: Hwan-Rong Lin, Hung-Chang Hsu
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Patent number: 6437575Abstract: A low-voltage detecting circuit for power sources is based upon the relation of the discharge time of a capacitor and the measured voltage value to determine whether the voltage level of the power source is too low. The voltage detecting circuit comprises a charge/discharge module and a discharge detecting module, wherein one terminal of said charge/discharge module is connected to the voltage to be measured. The discharge time of capacitor depends on the voltage to be measured. In other words, the voltage to be measured can be detected by calculating the discharge time of capacitor. Furthermore, the present invention provides a simplified circuit so as to reduce the fabrication cost.Type: GrantFiled: May 24, 2000Date of Patent: August 20, 2002Inventors: Hwan-Rong Lin, Huang-Hsiao Kao, Hung-Chang Hsu
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Publication number: 20020091952Abstract: A detection apparatus for use in a touch pad, for detecting the coordinates indicated by a user on the touch pad and the behavior of the user on the touch pad. The touch pad includes an X-layer and a Y-layer, and the X- and Y-layers are planar resistors. The detection apparatus has a sleep mode and an operative mode. When the user touches the touch pad, the X- and Y-layers are electrically coupled at a touch point. The detection apparatus includes a central processor, a coordinate detecting unit, an analog-to-digital converting unit, and a wake-up unit. The coordinate detecting unit is used to determine and output an X-coordinate voltage and a Y-coordinate voltage, wherein the X- and Y-coordinate voltages correspond to the touch point. The analog-to-digital converting unit is used to convert the X- and Y-coordinate voltages into an X-coordinate and a Y-coordinate, and to output the X and Y-coordinate.Type: ApplicationFiled: December 31, 2001Publication date: July 11, 2002Inventors: Hwan-Rong Lin, Hung-Chang Hsu
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Patent number: 5819108Abstract: A method for writing software into a programmable memory within a peripheral apparatus initiated by a host computer is provided. The host computer issues a software write command and the peripheral apparatus includes a microcontroller connected to the host computer via an interface. A data line and an address line are provided to connect the microcontroller and the programmable memory. The method comprises the following steps: (1) providing a supervisory program within the programmable memory or the microcontroller, the supervisory program including a software write instruction; (2) the microcontroller executing the software write instruction and down-loading the software from the host computer via the interface; and (3) via the data and address line, performing the write operation of the control software to the programmable memory.Type: GrantFiled: October 17, 1996Date of Patent: October 6, 1998Assignee: Acer Peripherals, Inc.Inventors: Hung-Chang Hsu, Chi-Cheng Lin, Meng-Shin Yen
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Patent number: 5633656Abstract: An apparatus for controlling an on-screen menu for television and display monitors. The apparatus includes a first data bus having a plurality of data lines including a least significant bit line. The first data bus transmits display information, the display information including alphanumeric data and attribute data relating to the parameters of the on-screen menu. A display buffer for storing both types of display information is coupled to the first data bus. The display buffer generates the alphanumeric data when a select signal is in a prescribed logic state, and generates the attribute data when the select signal is the complement of the prescribed logic state. A latch circuit for generating the select signal is coupled to the first data bus. By generating the select signal, the latch circuit causes the display buffer to generate the attribute data at a different time from the alphanumeric data. The latch circuit may then latch the attribute data by means of its connection to the first data bus.Type: GrantFiled: May 5, 1993Date of Patent: May 27, 1997Assignee: Acer Peripherals, Inc.Inventors: Hung-Chang Hsu, Chyi-Cheng Lin
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Patent number: 5574891Abstract: A method for managing the input codes from the keyboard and the point device and an apparatus thereof are provided. When the computer system is not coupled to a PS/2 mouse and a hybrid keyboard is found to be connected to the computer system, the method first requests the hybrid keyboard to send a leading code designated to the pointing device. Afterwards, the method detects whether an input code from the hybrid keyboard has a leading code. And if there is a leading code, the method emulates the input code as a PS/2 mouse code and sends the emulated PS/2 mouse code to the computer system.Type: GrantFiled: September 27, 1994Date of Patent: November 12, 1996Assignee: Acer Peripherals, Inc.Inventors: Hung-Chang Hsu, Jui-Ho Chen