Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

Abstract: A semiconductor includes a substrate, a semiconductor fin, an STI structure, a fin sidewall spacer, and a doped silicon layer. The semiconductor fin extends from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The fin sidewall spacer extends along a middle portion of the semiconductor fin that is above the lower portion of the semiconductor fin. The doped silicon layer wraps around three sides of an upper portion of the semiconductor fin that is above the middle portion of the semiconductor fin.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

Abstract: A semiconductor includes a substrate, a semiconductor fin, an STI structure, a fin sidewall spacer, and a doped silicon layer. The semiconductor fin extends from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The fin sidewall spacer extends along a middle portion of the semiconductor fin that is above the lower portion of the semiconductor fin. The doped silicon layer wraps around three sides of an upper portion of the semiconductor fin that is above the middle portion of the semiconductor fin.

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.

Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A MEOL structure is formed on an etch stop layer. A patterned masking layer with at least one opening is formed on the MEOL structure and a first etching process is performed to form a trench in the MEOL structure. A second etching process is performed to modify at least one sidewall of the trench.

Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A MEOL structure is formed on an etch stop layer. A patterned masking layer with at least one opening is formed on the MEOL structure and a first etching process is performed to form a trench in the MEOL structure. A second etching process is performed to modify at least one sidewall of the trench.

Abstract: The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated method of formation. In some embodiments, the integrated circuit is formed by forming a first work function metal layer directly on a high-k dielectric layer. Then the first work function metal layer is patterned to be left within a first gate region of a first device region and to be removed within a second gate region of a second device region. Thereby, the first work function metal layer is patterned directly on the high-k dielectric layer, using the high-k dielectric layer as an etch stop layer, and the patterning window is improved.

Abstract: The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated method of formation. In some embodiments, the integrated circuit is formed by forming a first work function metal layer directly on a high-k dielectric layer. Then the first work function metal layer is patterned to be left within a first gate region of a first device region and to be removed within a second gate region of a second device region. Thereby, the first work function metal layer is patterned directly on the high-k dielectric layer, using the high-k dielectric layer as an etch stop layer, and the patterning window is improved.

Abstract: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.

Abstract: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.