Abstract: A secondary-side control method of a flyback power converter includes a primary controller included in the flyback power converter generating a first gate control signal to turn on a power switch at a first predetermined valley of a first voltage after the primary controller enters a start-up mode; and a secondary controller included in the flyback power converter generating a trigger pulse to a synchronous switch at a second predetermined valley of a second voltage to make the primary controller enter a secondary-side control mode from the start-up mode after the secondary controller detects a first coupling voltage corresponding to the first gate control signal on the second voltage.

Abstract: A diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array. Each of the light emitting diodes includes a stack of functional layers includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer located between the first semiconductor layer and the second semiconductor layer. At least one of the light emitting diodes includes a first current limiting region covering at least a portion of the first semiconductor layer, the light emitting layer or the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are disposed at the same side of the first semiconductor layer.

Abstract: A stacked transistor arrangement and process of manufacture thereof are provided. Switched electrodes of first and second transistor chips are accessible on opposite sides of the first and second transistor chips. The first and second transistor chips are stacked one on top of the other. Switched electrodes of adjacent sides of the transistor chips are coupled together by a conductive layer positioned between the first and second transistor chips. Switched electrodes on sides of the first transistor chip and the second transistor chip that are opposite the adjacent sides are coupled to a lead frame by bond wires or solder bumps.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create a device with very high breakdown voltage and very low leakage current. This structure is extended to multiple deep trenches and shallow trenches alternating each other.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create a device with very high breakdown voltage and very low leakage current. This structure is extended to multiple deep trenches and shallow trenches alternating each other.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: Methods for manufacturing a MOSFET device for high voltage application are disclosed to solve less-than-90-degree trench angle problem. In one embodiment, the trenches in a MOSFET device are filled with different concentrations of P? epitaxial material at different stages to improve charge balance. In an alternative embodiment, several N? epitaxial layers with different concentrations are created before etching trenches filled with P? epitaxial material. Yet in another embodiment, a reverse deep trench process creates a P? epitaxial layer first, and etches trenches to be filled with N? epitaxial and act as active region during device operation, leaving the remaining P? epitaxial columns as non-active regions. The final device structure of the remaining P? epitaxial columns is similar to the traditional P? epitaxial trenches.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N? epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N? epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: A method for removing air micro-bubbles from photoresist used to purge a new photoresist filter is disclosed. The method includes flowing photoresist through a photoresist filter to remove air trapped in the photoresist filter, where the trapped air forms air micro-bubbles in the photoresist; collecting, in a buffer tank, the photoresist with air micro-bubbles; removing, in the buffer tank, the air micro-bubbles from the photoresist; and transferring the photoresist without air micro-bubbles from the buffer tank to photolithography equipment.

Abstract: The present disclosure describes a method that can be used to remove air micro-bubbles from photoresist used to purge a new photoresist filter. For example, the method includes flowing photoresist through a photoresist filter to remove air trapped in the photoresist filter, where the trapped air forms air micro-bubbles in the photoresist; collecting, in a buffer tank, the photoresist with air micro-bubbles; removing, in the buffer tank, the air micro-bubbles from the photoresist; and transferring the photoresist without air micro-bubbles from the buffer tank to photolithography equipment.

Abstract: Methods for manufacturing a MOSFET device for high voltage application are disclosed to solve less-than-90-degree trench angle problem. In one embodiment, the trenches in a MOSFET device are filled with different concentrations of P? epitaxial material at different stages to improve charge balance. In an alternative embodiment, several N? epitaxial layers with different concentrations are created before etching trenches filled with P? epitaxial material. Yet in another embodiment, a reverse deep trench process creates a P? epitaxial layer first, and etches wider conductive regions to be filled with N? epitaxial later, leaving the remaining P? epitaxial columns as non-conductive regions similar to the traditional P? epitaxial trenches.

Abstract: Apparatus, methods and other embodiments associated with a high speed and high breakdown voltage Schottky rectifier are disclosed. In one embodiment, the Schottky rectifier has three layers of N-type semiconductor, a first layer of highly doped N-type substrate at the bottom, a second layer of lightly doped epitaxial N-type material above the first layer, and a third layer of very low doping concentration N-type material created by converting the top shallow portion of the second layer without turning into P-type. The Schottky device further includes an enclosed deep trench structure close to the bottom of the second layer and can sustain high reverse bias voltage up to 2,000 volt.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N? epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N? epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: Apparatus, methods and other embodiments associated with a high speed and high breakdown voltage Schottky rectifier are disclosed. In one embodiment, the Schottky rectifier has three layers of N-type semiconductor, a first layer of highly doped N-type substrate at the bottom, a second layer of lightly doped epitaxial N-type material above the first layer, and a third layer of very low doping concentration N-type material created by converting the top shallow portion of the second layer without turning into P-type. The Schottky device further includes an enclosed deep trench structure close to the bottom of the second layer and can sustain high reverse bias voltage up to 2,000 volt.