Patents by Inventor Hung Cheng
Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12382135Abstract: A television (TV) use assessment system includes a TV decoder device operatively coupled to a television (TV) and configured to receive signals, decode the received signals and provide an output to be presented on a TV; a remote control device configured to receive inputs from a user and transmit input signals to the TV decoder device, wherein the TV decoder device is configured to receive the input signals from the remote control device and perform one or more functions encoded within the input signals; a camera configured to record user interactions with the system; and a performance evaluation apparatus configured to: receive the recording of the user interacting with the system and analyse the recording to generate an evaluation of the user interactions.Type: GrantFiled: January 8, 2024Date of Patent: August 5, 2025Assignee: Logistics and Supply Chain MultiTech R&D Centre LimitedInventors: Chun Hung Cheng, Ka Man Ng, Tsz Kin Chan, Chi Fung Chan, Woon Kwai Ngai
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Publication number: 20250246558Abstract: Semiconductor-on-insulator (SOI) structures with variable resistivity epitaxial semiconductor layers and methods of making the same are disclosed. The SOI structures may include customized resistivity profiles without changing the epitaxial structure of vendor-supplied base materials or requiring the development of new etching chemistries. An SOI structure may be formed by forming a second epitaxial semiconductor layer over a first epitaxial semiconductor layer on a first substrate, where the resistivity of the second epitaxial semiconductor layer is different than the resistivity of the first epitaxial semiconductor layer, forming a dielectric capping layer over the second epitaxial semiconductor layer, bonding the dielectric capping layer to a second dielectric capping layer on a second substrate, and removing the first substrate to provide the SOI structure. An optional third epitaxial semiconductor layer may be formed over the first epitaxial semiconductor layer.Type: ApplicationFiled: January 29, 2024Publication date: July 31, 2025Inventors: Yun-Chi Wu, Po-Wei Liu, Ping-Cheng Li, Yu-Hung Cheng, Yung-Lung Lin
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Publication number: 20250236985Abstract: An electroplating apparatus is adapted to electroplate an object to be plated having through holes. The electroplating apparatus includes a plating tank, a first anode plate parallel to a second anode plate in the plating tank, a cathode plate connected to the object to be plated, a first sensing module, and a second sensing module. The cathode plate and the object to be plated are in the plating tank and between the first anode plate and the second anode plate. The first sensing module includes a light source between the object to be plated and the first anode plate, and a light sensor between the object to be plated and the second anode plate. The second sensing module includes a first electrical sensor between the object to be plated and the first anode plate, and a second electrical sensor between the object to be plated and the second anode plate.Type: ApplicationFiled: March 25, 2024Publication date: July 24, 2025Applicant: Industrial Technology Research InstituteInventors: Yiu-Hsiang Chang, Ya-Hung Cheng
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Patent number: 12363513Abstract: The invention provides a drainage network monitoring system. The system comprises a sensing module for detecting one or more conditions at a location in the drainage network; a processing module for processing data received from the sensing module; a wireless communications module for communicating the processed data substantially in real-time to one or more wireless devices including a wireless notification device configured to issue notification information to users, wherein the wireless communications module utilizes a narrow bandwidth, low power wireless communications protocol to communicate processed data to the wireless notification device, and wherein the sensing module has a standalone power supply.Type: GrantFiled: March 15, 2023Date of Patent: July 15, 2025Assignee: Logistics and Supply Chain MultiTech R&D Centre LimitedInventors: Chun Hung Cheng, Ho Lam, Shiu Kee Luk, Kwong Tim Chan, Hoi Shun Tam
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Publication number: 20250222950Abstract: Methods and systems for assisting a vehicle to park using mixed-domain image data. Image-domain data is generated based on raw image data received from a plurality of cameras mounted on a vehicle. A bird's-eye-view (BEV) image is generated based on the raw image data. BEV-domain data associated with the BEV image is generated, which includes data associated with parking landmarks in the parking zone. A tri-perspective view (TPV) and associated data can be generated. A computing system localizes the vehicle within the parking zone based on the BEV-domain data, the image-domain data, and the TPV-domain data to generate localization data. The computing system performs mapping of the parking zone based on all three image-domain data and the localization data. A motion sensor such as an inertial measurement unit (IMU) can generate data that is used to compensate the various domain data.Type: ApplicationFiled: January 5, 2024Publication date: July 10, 2025Inventors: Xinhua XIAO, Lihao WANG, Hung-Cheng HUANG, Rachid BENMOKHTAR
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Publication number: 20250227328Abstract: A television (TV) use assessment system includes a TV decoder device operatively coupled to a television (TV) and configured to receive signals, decode the received signals and provide an output to be presented on a TV; a remote control device configured to receive inputs from a user and transmit input signals to the TV decoder device, wherein the TV decoder device is configured to receive the input signals from the remote control device and perform one or more functions encoded within the input signals; a camera configured to record user interactions with the system; and a performance evaluation apparatus configured to: receive the recording of the user interacting with the system and analyse the recording to generate an evaluation of the user interactions.Type: ApplicationFiled: January 8, 2024Publication date: July 10, 2025Inventors: Chun Hung Cheng, Ka Man Ng, Tsz Kin Chan, Chi Fung Chan, Woon Kwai Ngai
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Publication number: 20250225905Abstract: A method is provided for controlling subpixel luminance of a display screen. A driver circuit performs a first PWM on a subpixel based on a grayscale value of the subpixel when the grayscale value falls within a first grayscale range. When the first PWM is performed, the subpixel is driven to emit light at a first luminance when the subpixel is turned on. The driver circuit performs a second PWM on the subpixel based on the grayscale value when the grayscale value falls within a second grayscale range that is separate from and lower than the first grayscale range. When the second PWM is performed, the subpixel is driven to emit light at a second luminance when the subpixel is turned on. The second luminance is 2?N times the first luminance, and N is a positive integer.Type: ApplicationFiled: January 5, 2024Publication date: July 10, 2025Inventor: Hung-Cheng Kuo
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Patent number: 12349518Abstract: A micro LED structure includes a first micro LED chip having opposite first and second sides, a second micro LED chip adjacent to the first side of the second micro LED chip, a third micro LED chip adjacent to the first side of the first micro LED chip, and optical structures respectively over the first micro LED chip, the second micro LED chip and the third micro LED chip. Each of the first, second and third micro LED chip includes a semiconductor stack, a metal pad and a reflective coating layer. The semiconductor stack includes a first semiconductor layer, an active layer in contact with the first semiconductor layer, and a second semiconductor layer in contact with the active layer. The metal pad is in contact with the first semiconductor layer, and the reflective coating layer is disposed around sidewalls of the semiconductor stack.Type: GrantFiled: December 28, 2023Date of Patent: July 1, 2025Assignee: Lextar Electronics CorporationInventors: Kai-Hung Cheng, Fu-Han Ho
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Publication number: 20250210177Abstract: Electronic system and physiological monitoring method are provided. The electronic system includes a camera, an auxiliary feature sensor, and an accelerator. The camera is configured to take a facial image of a user. The auxiliary feature sensor is configured to sense an auxiliary feature of the user. The accelerator is configured to calculate an emotional status of the user according to the facial image. When it is determined that the emotional status meets a preset emotional status, the accelerator is configured to calculate an emotional level of the user by analyzing the auxiliary feature, and determine whether to issue an alert signal accordingly.Type: ApplicationFiled: March 22, 2024Publication date: June 26, 2025Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.Inventors: Hung-Cheng Chen, Shu Jen Lin, Yi Tse Chen, Chiang Lung Lin
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Patent number: 12342737Abstract: A RRAM device includes a bottom electrode, a resistive material layer, atop electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming the RRAM device is also provided.Type: GrantFiled: November 8, 2023Date of Patent: June 24, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
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Patent number: 12329046Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.Type: GrantFiled: May 23, 2022Date of Patent: June 10, 2025Assignee: United Microelectronics Corp.Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
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Publication number: 20250155609Abstract: An optical module is provided. The optical module includes a resin package, a lens and a light emitting element. The resin package has a receiving groove. The lens is disposed on the resin package, and the lens includes a light emitting surface, a light entering surface, and a central axis, wherein the light entering surface has an asymmetric structure. The light emitting element is disposed in the receiving groove, wherein the light emitting element is disposed deviated from the central axis of the lens.Type: ApplicationFiled: November 5, 2024Publication date: May 15, 2025Inventors: Kai-Hung CHENG, Ku-Cheng LIN, Chun-Min LIN, Wei-Yi HSU
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Publication number: 20250151383Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.Type: ApplicationFiled: December 26, 2024Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chen HO, Hung Chih HU, Hung Cheng YU, Ju Ru HSIEH
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Publication number: 20250151255Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.Type: ApplicationFiled: January 10, 2025Publication date: May 8, 2025Inventors: Yu-Ping HSIAO, Cheol-Soo PARK, Chun-Hung CHENG, Wei-Chieh CHUANG, Wei-Chao CHOU, Yen-Min JUAN
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Publication number: 20250149104Abstract: A memory testing method includes the operations of: generating test pattern data, a test address and reference data by a pattern generating circuit; performing a built-in self-test (BIST) according to the test pattern, the test address and the reference data by multiple memory modules to generate multiple test results; generating an indicator signal according to the multiple test results; when a first test result among the multiple test results indicates a fault, retaining the test address by the pattern generating circuit in response to the indicator signal, and testing, according to the test address and multiple sets of predetermined pattern data, a first memory module among the multiple memory modules that corresponds to the first test result to generate a localization test result; and determining a faulty memory cell in the first memory module according to the localization test result.Type: ApplicationFiled: October 25, 2024Publication date: May 8, 2025Inventors: Cheng Jie ZHU, Cheng Hung TSAI, Kuei Hung CHENG, Chia Ho PAN, Jian Na SHEN
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Publication number: 20250149851Abstract: A laser module is provided. The laser module includes a substrate, a laser diode and a diffuser. The substrate has a surface and a base plane, wherein the base plane is parallel to the surface. The laser diode is disposed on the surface. The diffuser is disposed above the laser diode, wherein an included angle is formed between the diffuser and the base plane, and the included angle is greater than 5 degrees.Type: ApplicationFiled: November 1, 2024Publication date: May 8, 2025Inventors: Yi-Min CHEN, Kai-Hung CHENG, Ming-Jing LEE, Jung-Tang CHU
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Patent number: 12295191Abstract: A light emitting-diode (LED) display device is provided. The display device comprises plural pixels arranged in array and each pixel includes at least one LED chip. The LED chip is disposed at a cavity of a black matrix (BM) layer and electrical connected to a transistor of a circuit substrate, wherein the transistor is below the BM layer.Type: GrantFiled: September 16, 2021Date of Patent: May 6, 2025Assignee: VISIONLABS CORPORATIONInventors: Hung-Cheng Lin, Hung-Kuang Hsu, Hua-Chen Hsu
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Publication number: 20250141135Abstract: An electrical connector includes: an insulating housing comprising a mating slot; a row of lower terminals arranged along a first direction and located at a lower side of the mating slot, each of the lower terminals including a fixing portion, an elastic arm, a soldering portion, the row of lower terminals including plural pairs of first signal terminals, plural pairs of second signal terminals, and plural grounding terminals, the pairs of first signal terminals and the pairs of second signal terminals being arranged alternately with each other and being separated by the grounding terminals; and a row of upper terminals located at an upper side of the mating slot, wherein, viewed in the first direction, the first signal terminals are aligned with each other, the second signal terminals are aligned with each other, and the second signal terminals protrude deeper into the mating slot than the first signal terminals.Type: ApplicationFiled: October 25, 2024Publication date: May 1, 2025Inventors: QIN-XIN CAO, Hung-Cheng LIAO, Hsuan-Ping CHIANG
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Patent number: 12288814Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.Type: GrantFiled: January 24, 2024Date of Patent: April 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
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Publication number: 20250132696Abstract: The present invention provides a magnetic power machine comprising a path portion, a rotor portion and a stator portion, wherein a rolling path is provided around the path portion; the rotor portion is provided around and outside the path portion and capable of rotating, and has an output shaft on one end that outputs power; a plurality of movable rods are provided on the rotor portion; a force-receiving arm and a roller are respectively provided on a top and a bottom of each of the movable rods; the roller moves along the rolling path; the force-receiving arm unfolds or folds as the roller moves up or down on the rolling path; the stator portion is provided around and outside the rotor portion; a plurality of force-exerting arms are provided opposite to the force-receiving arms on an inner edge of the stator portion; a magnetic force-exerting unit of single-sheet N-S arrangement and a magnetic force-receiving unit of triple-sheet N-S arrangement are respectively provided on the force-exerting arm and the forType: ApplicationFiled: October 20, 2023Publication date: April 24, 2025Inventors: Chien-Yu Hsu, Po-Lin Hsu, Yung-Hung Cheng