Abstract: A voltage generating circuit includes: (1) a driving unit having an input terminal and an output terminal, wherein the input terminal is configured to receive an input signal, wherein when the input signal is at a first logic level, power is configured to be charged from a first voltage terminal to the output terminal, and when the input signal is at a second logic level, power is configured to be discharged from the output terminal to a second voltage terminal; (2) a first switch configured to couple the second voltage terminal to a capacitance-compensating terminal based on the input signal; (3) a compensating capacitor configured to be coupled between the capacitance-compensating terminal and a third voltage terminal; and (4) a second switch configured to couple the capacitance-compensating terminal to a fourth voltage terminal based on the input signal.

Abstract: A voltage generating circuit includes: (1) a driving unit having an input terminal and an output terminal, wherein the input terminal is configured to receive an input signal, wherein when the input signal is at a first logic level, power is configured to be charged from a first voltage terminal to the output terminal, and when the input signal is at a second logic level, power is configured to be discharged from the output terminal to a second voltage terminal; (2) a first switch configured to couple the second voltage terminal to a capacitance-compensating terminal based on the input signal; (3) a compensating capacitor configured to be coupled between the capacitance-compensating terminal and a third voltage terminal; and (4) a second switch configured to couple the capacitance-compensating terminal to a fourth voltage terminal based on the input signal.

Abstract: An analog-to-digital (A/D) converting device according to the idea of the vernier caliper is provided. First, an analog signal is input into a primary A/D converting circuit to obtain a most significant bits (MSBs) of the digital signal. Then, the MSBs are input into a secondary A/D converting circuit to obtain a least significant bits (LSBs) of digital signal. Finally, the digital signal is obtained by merging the MSBs with the LSBs. Compared with the conventional flash A/D converting device, the present invention significantly reduces the quantity of the required components (for example, the amount of resistors and comparators), such that cost and power consumption are reduced. Compared with the conventional two-step A/D converting device, the present invention effectively eliminates the loading effect and provides a faster speed of signal conversion.

Abstract: An equalizer for a serial data communication receiver includes: a first transistor including a first input terminal, a first output terminal, and a first equalization terminal; a second transistor including a second input terminal, a second output terminal, and a second equalization terminal; a first resistor coupled to the first output terminal of the first transistor; a second resistor coupled to the second output terminal of the second transistor; a third resistor coupled to the first equalization terminal of the first transistor; a fourth resistor coupled between the second equalization terminal of the second transistor and the third resistor; a current source coupled between the third resistor and the fourth resistor; a first capacitor coupled to the first equalization terminal of the first transistor; and a second capacitor coupled to the second equalization terminal of the second transistor.

Abstract: A driving circuit for outputting high-frequency signal. The first NMOS transistor includes a first drain coupled to a first voltage level, a first gate coupled to the output terminal of the first operational amplifier and a first source coupled to the input terminal of the first operational amplifier. The first PMOS transistor includes a second drain coupled to a second voltage level, a second gate coupled to the output terminal of the second operational amplifier and a second source coupled to the input terminal of the second operational amplifier. The matching resistor having a predetermined resistance is coupled between the first source and the second source. The second NMOS transistor includes a third drain coupled to the first voltage level, a third gate coupled to the output terminal of the first operational amplifier and a third source.