Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A network switch fabric is provided for a clustering system to facilitate flexibility of network-related interconnection selection and system scalability. The network switch fabric includes replaceable network switch(s) and network interface(s) selectively configured on a base board. Multiple types of interconnection protocols with similar characteristics will be able to implement on a common infrastructure of network switch fabric. A pass through card operating as a network interface is also applicable on the network switch fabric to directly connect with an external network. The pass through card allows the network switch fabric supporting the clustering system to be scalable, thereby capable of supporting a large-scale cluster computing.

Abstract: A bandgap reference circuit having a low sensitivity to temperature and supplied voltage installs a compensation circuit on a bandgap reference circuit to substitute a prior art that uses a resistor to match the circuit startup purpose and solve the problem of startup error caused by the manufacturing error. The bandgap reference circuit includes a first amplifier, a second amplifier, and a reference circuit having a plurality of transistors and a plurality of bipolar junction transistors, and the bandgap reference circuit is electrically connected to a same supplied power of which the reference circuit is electrically connected and also includes a plurality of transistors and a compensation circuit of the second amplifier, so as to output a stable startup voltage which has a low sensitivity to the change of temperature and the change of supplied voltage.

Abstract: A network switch fabric is provided for a clustering system to facilitate flexibility of network-related interconnection selection and system scalability. The network switch fabric includes replaceable network switch(s) and network interface(s) selectively configured on a base board. Multiple types of interconnection protocols with similar characteristics will be able to implement on a common infrastructure of network switch fabric. A pass through card operating as a network interface is also applicable on the network switch fabric to directly connect with an external network. The pass through card allows the network switch fabric supporting the clustering system to be scalable, thereby capable of supporting a large-scale cluster computing.

Abstract: A bandgap reference circuit having a low sensitivity to temperature and supplied voltage installs a compensation circuit on a bandgap reference circuit to substitute a prior art that uses a resistor to match the circuit startup purpose and solve the problem of startup error caused by the manufacturing error. The bandgap reference circuit includes a first amplifier, a second amplifier, and a reference circuit having a plurality of transistors and a plurality of bipolar junction transistors, and the bandgap reference circuit is electrically connected to a same supplied power of which the reference circuit is electrically connected and also includes a plurality of transistors and a compensation circuit of the second amplifier, so as to output a stable startup voltage which has a low sensitivity to the change of temperature and the change of supplied voltage.

Abstract: A bandgap reference circuit having a low sensitivity to temperature and supplied voltage installs a compensation circuit on a bandgap reference circuit to substitute a prior art that uses a resistor to match the circuit startup purpose and solve the problem of startup error caused by the manufacturing error. The bandgap reference circuit includes a first amplifier, a second amplifier, and a reference circuit having a plurality of transistors and a plurality of bipolar junction transistors, and the bandgap reference circuit is electrically connected to a same supplied power of which the reference circuit is electrically connected and also includes a plurality of transistors and a compensation circuit of the second amplifier, so as to output a stable startup voltage which has a low sensitivity to the change of temperature and the change of supplied voltage.

Abstract: A bandgap reference circuit having a low sensitivity to temperature and supplied voltage installs a compensation circuit on a bandgap reference circuit to substitute a prior art that uses a resistor to match the circuit startup purpose and solve the problem of startup error caused by the manufacturing error. The bandgap reference circuit includes a first amplifier, a second amplifier, and a reference circuit having a plurality of transistors and a plurality of bipolar junction transistors, and the bandgap reference circuit is electrically connected to a same supplied power of which the reference circuit is electrically connected and also includes a plurality of transistors and a compensation circuit of the second amplifier, so as to output a stable startup voltage which has a low sensitivity to the change of temperature and the change of supplied voltage.

Abstract: An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.

Abstract: An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.

Abstract: A package of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the chip, in which the semiconductor chip is characterized at the bonding pads being positioned in at least four rows along each side of the chip, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads.

Abstract: An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.

Abstract: An internal circuit structure of a semiconductor chip with array-type bonding pads The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electrostatic discharge clamping circuit ring between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Each of the signal circuit macros is positioned to align to the corresponding bonding pads.

Abstract: A package of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the chip, in which the semiconductor chip is characterized at the bonding pads being positioned in at least four rows along each side of the chip, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads.