Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: A diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array. Each of the light emitting diodes includes a stack of functional layers includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer located between the first semiconductor layer and the second semiconductor layer. At least one of the light emitting diodes includes a first current limiting region covering at least a portion of the first semiconductor layer, the light emitting layer or the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the first electrode and the second electrode are disposed at the same side of the first semiconductor layer.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: A diode array is provided. The diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array, wherein each of the light emitting diodes includes a stack of functional layers comprising a first type semiconductor layer, a second type semiconductor layer, and a light emitting layer located between the first type semiconductor layer and the second type semiconductor layer, wherein at least one of the light emitting diodes includes: a first current limiting region abutting a vertically extending boundary of the second semiconductor layer; wherein, with respect to a top down view, the first current limiting region is formed about an outer edge of the light emitting diode and an outer perimeter of the first current limiting region is equal to or less than 400 micrometers (?m).

Abstract: A light emitting-diode (LED) display device is provided. The display device comprises plural pixels arranged in array and each pixel includes at least one LED chip. The LED chip is disposed at a cavity of a black matrix (BM) layer and electrical connected to a transistor of a circuit substrate, wherein the transistor is below the BM layer.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A diode array is provided. The diode array includes a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array, wherein each of the light emitting diodes includes a stack of functional layers comprising a first type semiconductor layer, a second type semiconductor layer, and a light emitting layer located between the first type semiconductor layer and the second type semiconductor layer, wherein at least one of the light emitting diodes includes: a first current limiting region abutting a vertically extending boundary of the second semiconductor layer; wherein, with respect to a top down view, the first current limiting region is formed about an outer edge of the light emitting diode and an outer perimeter of the first current limiting region is equal to or less than 400 micrometers (?m).

Abstract: Processes for obtaining a semiconductor nanodevice comprising a substrate, onto which patterned metal-oxide thin films having semiconductor properties are deposited, are provided, as well as semiconductor devices comprising them. The present invention belongs to the field of semiconductor nanodevices.

Abstract: The present invention discloses a graphene platelet fabrication method, which comprises Step (A): providing a highly-graphitized graphene having a graphitization degree of 0.8-1.0; and Step (B): providing a shear force acting on the highly-graphitized graphene to separate the highly-graphitized graphene into graphene platelets, wherein the graphene platelets have a length of 10-500 ?m and a width of 10-500 ?m and have a single-layer or multi-layer structure. The present invention also discloses a graphene platelet fabricated according to the abovementioned method.

Abstract: A heat conducting composite material includes a matrix and a graphene sheet. The graphene sheet has a two-dimensional planar structure, and a basal plane of the graphene sheet has a lateral size between 0.1 nm and 100 nm such that the graphene sheet has a quantum well structure. When radiation energy passes through the heat conducting composite material, the radiation energy is converted into infrared light by the quantum well structure of the graphene sheet to achieve high radiating efficiency. A light-emitting diode (LED) having the heat conducting composite material and capable of achieving a heat dissipation effect is further disclosed.

Abstract: A medical drill is disclosed, which is made of amorphous alloy, the amorphous alloy is a Ti-based amorphous alloy which comprises titanium in 40 at % or above, wherein the tensile strength of the medical drill is 1600-2600 MPa, and the Vicker's hardness of the medical drill is 600-800.

Abstract: A medical drill is disclosed, which is made of amorphous alloy, the amorphous alloy is zirconium amorphous alloy comprising 45 at % or above of zirconium, wherein the tensile strength of the medical drill is 1500-2500 Mpa, and the Vicker's hardness of the medical drill is 400-750. Moreover, a medical drill made of titanium amorphous alloy is also disclosed.

Abstract: The present invention relates to a porous amorphous alloy artificial joint and a manufacturing method thereof The porous amorphous alloy artificial joint is formed of at least one of amorphous alloy compounds represented by Formula 1 to Formula 4 as described in the present specification.