Patents by Inventor Hung Cheng YU

Hung Cheng YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218129
    Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chen Ho, Hung Chih Hu, Hung Cheng Yu, Ju Ru Hsieh
  • Patent number: 11721694
    Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Hung Chih Hu, Hung Cheng Yu, Ju Ru Hsieh
  • Publication number: 20220336450
    Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Yi-Chen HO, Hung Chih HU, Hung Cheng YU, Ju Ru HSIEH
  • Publication number: 20210272951
    Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Yi-Chen HO, Hung Chih HU, Hung Cheng YU, Ju Ru HSIEH