Patents by Inventor Hung-Chi Pai

Hung-Chi Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070232069
    Abstract: A CMP apparatus therefor is provided. First, a substrate including a semiconductor structure, a liner layer over the semiconductor structure and a metal layer over the liner layer is provided. Next, a metal polishing step is performed to polish the metal layer until a portion of the liner layer is exposed. Next, a buffing step is performed to remove any contaminants from the surface of the metal layer. Thereafter, a liner CMP step is performed to polish the liner layer.
    Type: Application
    Filed: May 27, 2007
    Publication date: October 4, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Yu Tseng, Chun-Ting Hu, Chu-Yi Hsieh, Hung-Chi Pai, Yung-Chieh Kuo
  • Publication number: 20070082490
    Abstract: An apparatus of chemical mechanical polishing has a polishing machine, a first thickness metrology and a second thickness metrology. The first thickness metrology is connected with the polishing machine, and the second thickness metrology is connected with the polishing machine. Since the thickness of the first material layer and the second material layer after polishing process can be separately measured by the first thickness metrology and the second thickness metrology in-situ, the difference of film thickness between wafers can be reduced.
    Type: Application
    Filed: October 6, 2005
    Publication date: April 12, 2007
    Inventors: Chun-Ting Hu, Chu-Yi Hsieh, Tzu-Yu Tseng, Yung-Chieh Kuo, Hung-Chi Pai
  • Publication number: 20070072426
    Abstract: A CMP process and a CMP apparatus therefor are provided. First, a substrate including a semiconductor structure, a liner layer over the semiconductor structure and a metal layer over the liner layer is provided. Next, a metal polishing step is performed to polish the metal layer until a portion of the liner layer is exposed. Next, a buffing step is performed to remove any contaminants from the surface of the metal layer. Thereafter, a liner CMP step is performed to polish the liner layer.
    Type: Application
    Filed: September 26, 2005
    Publication date: March 29, 2007
    Inventors: Tzu-Yu Tseng, Chun-Ting Hu, Chu-Yi Hsieh, Hung-Chi Pai, Yung-Chieh Kuo
  • Publication number: 20070060028
    Abstract: A CMP slurry delivery system includes a delivery pipe, a first slurry supply reservoir coupled to the delivery pipe for supplying an abrasive, a second slurry supply reservoir coupled to the delivery pipe for supplying a clean chemical, a third slurry supply reservoir coupled to the delivery pipe for supplying a corrosion inhibitor, and a fourth slurry supply reservoir for supplying an oxidizer.
    Type: Application
    Filed: October 30, 2006
    Publication date: March 15, 2007
    Inventors: Sheng-Yu Chen, Te-Sung Hung, Chi-Piao Cheng, Chung-Jung Cheng, Kaung-Wu Nieh, Po-Yuan Cheng, Jiann-Fu Chen, Chun-Ting Hu, Tzu-Yu Tseng, Tzu-Yi Hsieh, Hung-Chi Pai, Yung-Chieh Kuo
  • Publication number: 20060191871
    Abstract: A CMP slurry delivery system includes a delivery pipe, a first slurry supply reservoir coupled to the delivery pipe for supplying an abrasive, a second slurry supply reservoir coupled to the delivery pipe for supplying a clean chemical, a third slurry supply reservoir coupled to the delivery pipe for supplying a corrosion inhibitor, and a fourth slurry supply reservoir for supplying an oxidizer.
    Type: Application
    Filed: February 25, 2005
    Publication date: August 31, 2006
    Inventors: Sheng-Yu Chen, Te-Sung Hung, Chi-Piao Cheng, Chung-Jung Cheng, Kaung-Wu Nieh, Po-Yuan Cheng, Jiann-Fu Chen, Chun-Ting Hu, Tzu-Yu Tseng, Tzu-Yi Hsieh, Hung-Chi Pai, Yung-Chieh Kuo
  • Publication number: 20040203228
    Abstract: A semiconductor wafer including a substrate, a copper dual damascene structure positioned on the substrate, a dielectric layer covering the copper dual damascene structure, and a via hole positioned in the dielectric layer, the hole continuing to a surface of the copper layer. First, a tantalum nitride (TaN) layer is formed on a bottom surface within the via hole and on walls within the via hole. A titanium nitride (TiN) layer is then formed on the tantalum nitride layer. By performing a chemical vapor deposition (CVD) process, a tungsten layer is formed to cover a surface of the titanium nitride layer as well as to fill the via hole. Finally, a chemical mechanical polishing (CMP) process is performed to make a top of the tungsten layer in the via hole aligned with the surface of the dielectric layer so as to form a tungsten plug.
    Type: Application
    Filed: April 10, 2003
    Publication date: October 14, 2004
    Inventors: Ya-Hui Liao, Hung-Chi Pai, Ming-Jui Mao, Shu-En Lee