Patents by Inventor Hung-Chi Tsai

Hung-Chi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240233598
    Abstract: An image display method for handling a dynamic image signal including a plurality of continuous video frames, wherein the method includes steps as follows: Firstly, a first display parameter is output to display an Nth video frame of the plurality of continuous video frames according to a first attribute data of the Nth video frame. Then, at least one of (N+K)th video frame is detected, and when the at least one of the (N+K)th video frame has second attribute data, the first display parameter is output to display the at least one of the (N+K)th video frames. Subsequently, an (N+K+1)th video frame is detected, and when the (N+K+1)th video frame has the second attribute data, a second display parameter is output to display the (N+K+1)th video frame according to the second attribute data. Wherein, K is a positive integer greater than 1.
    Type: Application
    Filed: March 21, 2024
    Publication date: July 11, 2024
    Applicant: BENQ CORPORATION
    Inventors: Hung-Chi TSAI, Chen-Cheng HUANG
  • Patent number: 12001129
    Abstract: A light mixing module is provided. The light mixing module includes a first laser array, a second laser array, and one or more laser polarized fold mirrors. The first laser array is configured for emitting a plurality of polarized light beams having a first polarization state. The second array is configured for emitting a plurality of polarized light beams having the first polarization state. The second laser array is disposed opposite to the first laser array. The one or more laser polarized fold mirrors are disposed between the first laser array and the second laser array. The one or more laser polarized fold mirrors reflect the polarized light beams emitted by the first laser array and the polarized light beams emitted by the second laser array. Each one of the one or more laser polarized fold mirrors is configured to direct light beams from at least two different directions.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: June 4, 2024
    Assignee: BenQ Corporation
    Inventors: Kai-Jiun Wang, Hung-Chi Tsai, Shuang-Xi Lin
  • Patent number: 12002399
    Abstract: An image display method for handling a dynamic image signal including a plurality of continuous video frames, wherein the method includes steps as follows: Firstly, a first display parameter is output to display an Nth video frame of the plurality of continuous video frames according to a first attribute data of the Nth video frame. Then, at least one of (N+K)th video frame is detected, and when the at least one of the (N+K)th video frame has second attribute data, the first display parameter is output to display the at least one of the (N+K)th video frames. Subsequently, an (N+K+1)th video frame is detected, and when the (N+K+1)th video frame has the second attribute data, a second display parameter is output to display the (N+K+1)th video frame according to the second attribute data. Wherein, K is a positive integer greater than 1.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: June 4, 2024
    Assignee: BenQ Corporation
    Inventors: Hung-Chi Tsai, Chen-Cheng Huang
  • Patent number: 11948968
    Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hung-Chi Tsai
  • Publication number: 20240090204
    Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Inventor: HUNG-CHI TSAI
  • Publication number: 20240055521
    Abstract: The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventor: HUNG-CHI TSAI
  • Publication number: 20230403847
    Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.
    Type: Application
    Filed: August 15, 2023
    Publication date: December 14, 2023
    Inventor: HUNG-CHI TSAI
  • Publication number: 20230352588
    Abstract: The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 2, 2023
    Inventor: HUNG-CHI TSAI
  • Publication number: 20230333457
    Abstract: A light mixing module is provided. The light mixing module includes a first laser array, a second laser array, and one or more laser polarized fold mirrors. The first laser array is configured for emitting a plurality of polarized light beams having a first polarization state. The second array is configured for emitting a plurality of polarized light beams having the first polarization state. The second laser array is disposed opposite to the first laser array. The one or more laser polarized fold mirrors are disposed between the first laser array and the second laser array. The one or more laser polarized fold mirrors reflect the polarized light beams emitted by the first laser array and the polarized light beams emitted by the second laser array. Each one of the one or more laser polarized fold mirrors is configured to direct light beams from at least two different directions.
    Type: Application
    Filed: November 22, 2022
    Publication date: October 19, 2023
    Applicant: BENQ CORPORATION
    Inventors: Kai-Jiun WANG, Hung-Chi TSAI, Shuang-Xi LIN
  • Patent number: 11778812
    Abstract: The present disclosure relates to a method for forming a semiconductor device with a conductive cap layer over a conductive plug. The method includes forming a first word line and a second word line over a semiconductor substrate, and forming a dielectric layer covering the first word line and the second word line. The method also includes forming a conductive plug between the first word line and the second word line, wherein the conductive plug is surrounded by the dielectric layer. The method further includes removing a portion of the dielectric layer to partially expose a sidewall surface of the conductive plug, and forming a conductive cap layer covering a top surface and the sidewall surface of the conductive plug. In addition, the method includes forming a bit line over the conductive plug, wherein the bit line is electrically connected to the conductive plug through the conductive cap layer.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: October 3, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hung-Chi Tsai
  • Publication number: 20230301073
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a channel region positioned in the substrate, first impurity regions positioned in the substrate and respectively positioned on two ends of the channel region, a gate dielectric layer positioned on the channel region, a gate bottom conductive layer positioned on the gate dielectric layer, composite contacts respectively positioned on the first impurity regions, programmable insulating layers respectively positioned on the composite contacts, a top conductive layer positioned on the programmable insulating layers and electrically coupled to the gate bottom conductive layer. One of the plurality of composite contacts includes a protection liner having a U-shaped profile and a metal core in the protection liner.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventor: HUNG-CHI TSAI
  • Publication number: 20230197768
    Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Inventor: HUNG-CHI TSAI
  • Publication number: 20230136804
    Abstract: An image display method for handling a dynamic image signal including a plurality of continuous video frames, wherein the method includes steps as follows: Firstly, a first display parameter is output to display an Nth video frame of the plurality of continuous video frames according to a first attribute data of the Nth video frame. Then, at least one of (N+K)th video frame is detected, and when the at least one of the (N+K)th video frame has second attribute data, the first display parameter is output to display the at least one of the (N+K)th video frames. Subsequently, an (N+K+1)th video frame is detected, and when the (N+K+1)th video frame has the second attribute data, a second display parameter is output to display the (N+K+1)th video frame according to the second attribute data. Wherein, K is a positive integer greater than 1.
    Type: Application
    Filed: April 19, 2022
    Publication date: May 4, 2023
    Applicant: BENQ CORPORATION
    Inventors: Hung-Chi TSAI, Chen-Cheng HUANG
  • Patent number: 11610963
    Abstract: The present disclosure provides a semiconductor device structure with a bottom capacitor electrode having a crown-shaped structure and an interconnect portion and a method for forming the same. The semiconductor device structure includes a capacitor contact disposed over a semiconductor substrate, and a dielectric layer disposed over the capacitor contact. The semiconductor device structure also includes a patterned mask disposed over the dielectric layer, and a bottom capacitor electrode disposed over and electrically connected to the capacitor contact. The bottom capacitor electrode includes a base layer disposed between the capacitor contact and the dielectric layer, and a surrounding portion disposed over the base layer and along sidewalls of the dielectric layer and the patterned mask. The bottom capacitor electrode also includes a first interconnect portion disposed in the dielectric layer and substantially parallel to the base layer.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hung-Chi Tsai
  • Patent number: 11589020
    Abstract: A parameter adjusting method is applied to a projector having an ambient light sensor, a database and a digital micromirror device. The parameter adjusting method includes analyzing a detection signal generated by the ambient light sensor to acquire an environmental light datum, comparing the environmental light datum with a lookup table of the database to compute at least one compensation parameter, and adjusting an amount of reflection light generated by the digital micromirror device in accordance with the at least one compensation parameter for controlling the projector to output a calibrated projection image in response to compensation of the environmental light datum.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 21, 2023
    Assignee: BenQ Corporation
    Inventors: Hung-Chi Tsai, Chen-Cheng Huang
  • Publication number: 20230025690
    Abstract: A parameter adjusting method is applied to a projector having an ambient light sensor, a database and a digital micromirror device. The parameter adjusting method includes analyzing a detection signal generated by the ambient light sensor to acquire an environmental light datum, comparing the environmental light datum with a lookup table of the database to compute at least one compensation parameter, and adjusting an amount of reflection light generated by the digital micromirror device in accordance with the at least one compensation parameter for controlling the projector to output a calibrated projection image in response to compensation of the environmental light datum.
    Type: Application
    Filed: August 26, 2021
    Publication date: January 26, 2023
    Applicant: BENQ CORPORATION
    Inventors: Hung-Chi Tsai, Chen-Cheng Huang
  • Patent number: 11532506
    Abstract: The present disclosure provides an integrated circuit structure with dielectric isolation structure for reducing capacitive coupling and crosstalk between conductive features and a method for preparing the same. The integrated circuit structure includes a plurality of conductive structures disposed over a substrate; a plurality of dielectric structures disposed over the conductive structures; an inter-layer dielectric (ILD) layer disposed over sidewalls of the dielectric structures and sidewalls of the conductive structures, wherein the ILD layer, the dielectric structure and the conductive structure form an air spacer therebetween; and a dielectric isolation structure including a liner layer enclosing an air gap in the ILD layer.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: December 20, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hung-Chi Tsai
  • Publication number: 20220208955
    Abstract: The present disclosure provides a semiconductor device structure with a bottom capacitor electrode having a crown-shaped structure and an interconnect portion and a method for forming the same. The semiconductor device structure includes a capacitor contact disposed over a semiconductor substrate, and a dielectric layer disposed over the capacitor contact. The semiconductor device structure also includes a patterned mask disposed over the dielectric layer, and a bottom capacitor electrode disposed over and electrically connected to the capacitor contact. The bottom capacitor electrode includes a base layer disposed between the capacitor contact and the dielectric layer, and a surrounding portion disposed over the base layer and along sidewalls of the dielectric layer and the patterned mask. The bottom capacitor electrode also includes a first interconnect portion disposed in the dielectric layer and substantially parallel to the base layer.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventor: HUNG-CHI TSAI
  • Patent number: 11302814
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, two conductive features positioned apart from each other over the substrate, and a porous middle layer positioned between the two conductive features and adjacent to the two conductive features. A porosity of the porous middle layer is between about 25% and about 100%.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: April 12, 2022
    Assignee: NANYA TECHNOLOGY CORP.
    Inventor: Hung-Chi Tsai
  • Publication number: 20220059686
    Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate; forming two conductive features apart from each other over the substrate; forming a porous middle layer positioned between the two conductive features and adjacent to the two conductive features; depositing an energy-removable material between the two conductive features and adjacent to the two conductive features; and performing an energy treatment to transform the energy-removable material into a porous middle layer. The porosity of the porous middle layer is between about 25% and about 100%.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 24, 2022
    Inventor: HUNG-CHI TSAI