Patents by Inventor Hung-Chi Tsai
Hung-Chi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136226Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Li-Wei CHU, Ying-Chi SU, Yu-Kai CHEN, Wei-Yip LOH, Hung-Hsu CHEN, Chih-Wei CHANG, Ming-Hsing TSAI
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Patent number: 11948968Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.Type: GrantFiled: February 13, 2023Date of Patent: April 2, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hung-Chi Tsai
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Publication number: 20240090204Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventor: HUNG-CHI TSAI
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Patent number: 11915976Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.Type: GrantFiled: June 27, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Chu, Ying-Chi Su, Yu-Kai Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20240055521Abstract: The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventor: HUNG-CHI TSAI
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Publication number: 20230403847Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.Type: ApplicationFiled: August 15, 2023Publication date: December 14, 2023Inventor: HUNG-CHI TSAI
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Publication number: 20230352588Abstract: The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.Type: ApplicationFiled: July 11, 2023Publication date: November 2, 2023Inventor: HUNG-CHI TSAI
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Publication number: 20230333457Abstract: A light mixing module is provided. The light mixing module includes a first laser array, a second laser array, and one or more laser polarized fold mirrors. The first laser array is configured for emitting a plurality of polarized light beams having a first polarization state. The second array is configured for emitting a plurality of polarized light beams having the first polarization state. The second laser array is disposed opposite to the first laser array. The one or more laser polarized fold mirrors are disposed between the first laser array and the second laser array. The one or more laser polarized fold mirrors reflect the polarized light beams emitted by the first laser array and the polarized light beams emitted by the second laser array. Each one of the one or more laser polarized fold mirrors is configured to direct light beams from at least two different directions.Type: ApplicationFiled: November 22, 2022Publication date: October 19, 2023Applicant: BENQ CORPORATIONInventors: Kai-Jiun WANG, Hung-Chi TSAI, Shuang-Xi LIN
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Patent number: 11778812Abstract: The present disclosure relates to a method for forming a semiconductor device with a conductive cap layer over a conductive plug. The method includes forming a first word line and a second word line over a semiconductor substrate, and forming a dielectric layer covering the first word line and the second word line. The method also includes forming a conductive plug between the first word line and the second word line, wherein the conductive plug is surrounded by the dielectric layer. The method further includes removing a portion of the dielectric layer to partially expose a sidewall surface of the conductive plug, and forming a conductive cap layer covering a top surface and the sidewall surface of the conductive plug. In addition, the method includes forming a bit line over the conductive plug, wherein the bit line is electrically connected to the conductive plug through the conductive cap layer.Type: GrantFiled: April 30, 2021Date of Patent: October 3, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hung-Chi Tsai
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Publication number: 20230301073Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a channel region positioned in the substrate, first impurity regions positioned in the substrate and respectively positioned on two ends of the channel region, a gate dielectric layer positioned on the channel region, a gate bottom conductive layer positioned on the gate dielectric layer, composite contacts respectively positioned on the first impurity regions, programmable insulating layers respectively positioned on the composite contacts, a top conductive layer positioned on the programmable insulating layers and electrically coupled to the gate bottom conductive layer. One of the plurality of composite contacts includes a protection liner having a U-shaped profile and a metal core in the protection liner.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventor: HUNG-CHI TSAI
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Publication number: 20230197768Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventor: HUNG-CHI TSAI
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Publication number: 20230136804Abstract: An image display method for handling a dynamic image signal including a plurality of continuous video frames, wherein the method includes steps as follows: Firstly, a first display parameter is output to display an Nth video frame of the plurality of continuous video frames according to a first attribute data of the Nth video frame. Then, at least one of (N+K)th video frame is detected, and when the at least one of the (N+K)th video frame has second attribute data, the first display parameter is output to display the at least one of the (N+K)th video frames. Subsequently, an (N+K+1)th video frame is detected, and when the (N+K+1)th video frame has the second attribute data, a second display parameter is output to display the (N+K+1)th video frame according to the second attribute data. Wherein, K is a positive integer greater than 1.Type: ApplicationFiled: April 19, 2022Publication date: May 4, 2023Applicant: BENQ CORPORATIONInventors: Hung-Chi TSAI, Chen-Cheng HUANG
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Patent number: 11610963Abstract: The present disclosure provides a semiconductor device structure with a bottom capacitor electrode having a crown-shaped structure and an interconnect portion and a method for forming the same. The semiconductor device structure includes a capacitor contact disposed over a semiconductor substrate, and a dielectric layer disposed over the capacitor contact. The semiconductor device structure also includes a patterned mask disposed over the dielectric layer, and a bottom capacitor electrode disposed over and electrically connected to the capacitor contact. The bottom capacitor electrode includes a base layer disposed between the capacitor contact and the dielectric layer, and a surrounding portion disposed over the base layer and along sidewalls of the dielectric layer and the patterned mask. The bottom capacitor electrode also includes a first interconnect portion disposed in the dielectric layer and substantially parallel to the base layer.Type: GrantFiled: December 29, 2020Date of Patent: March 21, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hung-Chi Tsai
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Patent number: 11589020Abstract: A parameter adjusting method is applied to a projector having an ambient light sensor, a database and a digital micromirror device. The parameter adjusting method includes analyzing a detection signal generated by the ambient light sensor to acquire an environmental light datum, comparing the environmental light datum with a lookup table of the database to compute at least one compensation parameter, and adjusting an amount of reflection light generated by the digital micromirror device in accordance with the at least one compensation parameter for controlling the projector to output a calibrated projection image in response to compensation of the environmental light datum.Type: GrantFiled: August 26, 2021Date of Patent: February 21, 2023Assignee: BenQ CorporationInventors: Hung-Chi Tsai, Chen-Cheng Huang
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Publication number: 20230025690Abstract: A parameter adjusting method is applied to a projector having an ambient light sensor, a database and a digital micromirror device. The parameter adjusting method includes analyzing a detection signal generated by the ambient light sensor to acquire an environmental light datum, comparing the environmental light datum with a lookup table of the database to compute at least one compensation parameter, and adjusting an amount of reflection light generated by the digital micromirror device in accordance with the at least one compensation parameter for controlling the projector to output a calibrated projection image in response to compensation of the environmental light datum.Type: ApplicationFiled: August 26, 2021Publication date: January 26, 2023Applicant: BENQ CORPORATIONInventors: Hung-Chi Tsai, Chen-Cheng Huang
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Patent number: 11532506Abstract: The present disclosure provides an integrated circuit structure with dielectric isolation structure for reducing capacitive coupling and crosstalk between conductive features and a method for preparing the same. The integrated circuit structure includes a plurality of conductive structures disposed over a substrate; a plurality of dielectric structures disposed over the conductive structures; an inter-layer dielectric (ILD) layer disposed over sidewalls of the dielectric structures and sidewalls of the conductive structures, wherein the ILD layer, the dielectric structure and the conductive structure form an air spacer therebetween; and a dielectric isolation structure including a liner layer enclosing an air gap in the ILD layer.Type: GrantFiled: November 8, 2021Date of Patent: December 20, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hung-Chi Tsai
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Publication number: 20220208955Abstract: The present disclosure provides a semiconductor device structure with a bottom capacitor electrode having a crown-shaped structure and an interconnect portion and a method for forming the same. The semiconductor device structure includes a capacitor contact disposed over a semiconductor substrate, and a dielectric layer disposed over the capacitor contact. The semiconductor device structure also includes a patterned mask disposed over the dielectric layer, and a bottom capacitor electrode disposed over and electrically connected to the capacitor contact. The bottom capacitor electrode includes a base layer disposed between the capacitor contact and the dielectric layer, and a surrounding portion disposed over the base layer and along sidewalls of the dielectric layer and the patterned mask. The bottom capacitor electrode also includes a first interconnect portion disposed in the dielectric layer and substantially parallel to the base layer.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventor: HUNG-CHI TSAI
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Patent number: 11302814Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, two conductive features positioned apart from each other over the substrate, and a porous middle layer positioned between the two conductive features and adjacent to the two conductive features. A porosity of the porous middle layer is between about 25% and about 100%.Type: GrantFiled: January 23, 2020Date of Patent: April 12, 2022Assignee: NANYA TECHNOLOGY CORP.Inventor: Hung-Chi Tsai
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Publication number: 20220059686Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate; forming two conductive features apart from each other over the substrate; forming a porous middle layer positioned between the two conductive features and adjacent to the two conductive features; depositing an energy-removable material between the two conductive features and adjacent to the two conductive features; and performing an energy treatment to transform the energy-removable material into a porous middle layer. The porosity of the porous middle layer is between about 25% and about 100%.Type: ApplicationFiled: November 1, 2021Publication date: February 24, 2022Inventor: HUNG-CHI TSAI
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Publication number: 20220059400Abstract: The present disclosure provides an integrated circuit structure with dielectric isolation structure for reducing capacitive coupling and crosstalk between conductive features and a method for preparing the same. The integrated circuit structure includes a plurality of conductive structures disposed over a substrate; a plurality of dielectric structures disposed over the conductive structures; an inter-layer dielectric (ILD) layer disposed over sidewalls of the dielectric structures and sidewalls of the conductive structures, wherein the ILD layer, the dielectric structure and the conductive structure form an air spacer therebetween; and a dielectric isolation structure including a liner layer enclosing an air gap in the ILD layer.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventor: HUNG-CHI TSAI