Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.

Abstract: A soldering quality inspection method and a soldering quality inspection apparatus are provided. The soldering quality inspection method includes: acquiring an inspection image; calculating, by a processing device, a dyed area percentage of an area of a part of a soldering region in the inspection image that is dyed by a dye ink relative to an area of the soldering region, and determining whether the dyed area percentage is greater than a predetermined dyed percentage. When the dyed area percentage is determined to be equal to or less than the predetermined dyed percentage, a position under inspection is determined to be of good soldering quality, and a corresponding inspection result information is generated. When the dyed area percentage is determined to be greater than the predetermined dyed percentage, the position under inspection is determined to be of poor soldering quality, and the corresponding inspection result information is generated.

Abstract: An electronic device includes a casing, an antenna, and a connector. The casing includes a metal layer and a first slot and a second slot located on the metal layer. The metal layer includes a metal connecting segment, a first region, and a second region. The metal connecting segment is located between the first slot and the second slot, and the first region and the second region are separated by the first slot, the second slot, and the metal connecting segment. The antenna is connected to the first region, and the antenna is adapted to resonate at a frequency band. The connector is connected to the second region.

Abstract: An antenna module includes a ground radiator, a first antenna, and a second antenna. The first antenna includes a first feeding end, a first segment, a second segment, a third segment, and a fourth segment. A first area of the first antenna and a second area including a part of the first antenna and a part of the ground radiator resonate at a first frequency band. A third area of the first antenna and the second area resonate at a second frequency band. An area including a part of the second antenna, the third segment, the first segment, and the second segment resonates at the first frequency band. An area of the second antenna and an area including the part of the second antenna, a part of the third segment, and another part of the ground radiator resonate at the second frequency band.

Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: The present disclosure provides a customized module-wise bra with both aesthetic, comfort, and functions assisting a post-mastectomy subject to wear the bra and correct any postural distortion arising from imbalance due to loss of weight from the mastectomized breast. Also provided herein is a method for fabricating the customized module-wise bra according to the anatomical/physical characteristics of the subject based on various 3D printing, 3D body scanning and ultrasonography techniques.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: Embodiments of performing a photolithography process are provided. The method for performing the photolithography process includes providing a substrate and forming a photoresist layer over the substrate. The method further includes forming exposed photoresist portions by performing an exposure process on the photoresist layer. The method further includes performing a surface modifying treatment on the photoresist layer after the exposure process and removing the exposed photoresist portions by performing a developing process.

Abstract: Embodiments of performing a photolithography process are provided. The method for performing the photolithography process includes providing a substrate and forming a photoresist layer over the substrate. The method further includes forming exposed photoresist portions by performing an exposure process on the photoresist layer. The method further includes performing a surface modifying treatment on the photoresist layer after the exposure process and removing the exposed photoresist portions by performing a developing process.

Abstract: A process of automatically translating a high level programming language into a hardware description language (HDL), which can use a three-stage translation mechanism to generate the HDL codes corresponding to the functions described by the high level programming language. The first stage translates source codes coded by the high level programming language into an extended activity diagram (EAD). The second stage translates the EAD into a hardware component graph (HCG). The third stage generates the respective signal connections of HDL components according to all edges of the HCG, and outputs an HDL entity and architecture to a file in a string form, thereby completing the entire translation.

Abstract: A process of automatically translating an extended activity diagram (EAD) into a hardware component graph (HCG).

Abstract: A storage cabinet comprised of an upper cover, a frame, a base, a back mirror, and a rear panel. The frame is fabricated of steel tubing (hollow metal tubes) and active hinges are installed on the frame to provide for its folding, thereby simplifying packaging material cost. Slide slots are formed along the top edges of lateral frame members that provide for the installation and positioning of the back mirror and the rear panel. The overall design of the present invention reduces components to a bare minimum and is safe, convenient, facilitates DIY assembly, and lowers import and export shipping costs.

Abstract: This invention relates to an adjustable magnetic brake and in particular to one including an aluminum fan, a magnetic conducting ring enclosing the aluminum fan, a permanent magnet disposed within the aluminum fan, a fixing seat for keeping the permanent magnet in position, a sliding seat mounted in the fixing seat and provided with a bearing, a housing, bolts provided on one side of the fixing seat and extending out of the housing, a mounting plate connected with the bolts and a wire connected with the mounting plate such that when the wire is pulled outwards, the permanent magnet will be moved outwards.