Patents by Inventor Hung-Chieh Lin

Hung-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230018511
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 11539625
    Abstract: A packet processing system including an ingress unit, a detour launcher, a packet sequencer, a post-detour handler and an egress unit. The ingress unit is used to receive a packet. The detour launcher is used to detect a microburst according to at least a queue value and accordingly send the packet. The packet sequencer is used to attach a sequence number to the packet when the microburst emerges. The post-detoured handler is used to release the packet after the microburst has elapsed. The egress unit is used to output the packet processed by at least one member of a group consisting of the detour launcher, the packet sequencer and the post-detour handler.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 27, 2022
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Po-Jen Chen, Yu-Chieh Lin, Hung-Pin Wen, Chi-Hsiang Hung
  • Patent number: 11527476
    Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
  • Publication number: 20220382004
    Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Yu-Hsiang Hu, Chewn-Pu Jou, Feng-Wei Kuo
  • Patent number: 11508585
    Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Publication number: 20220365273
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Publication number: 20220365297
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20220367376
    Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
  • Publication number: 20220351948
    Abstract: An apparatus includes a chamber, a pedestal configured to receive and support a semiconductor wafer in the chamber, and an edge ring disposed over the pedestal. The edge ring includes a first portion having a first top surface, a second portion coupled to the first portion and having a second top surface lower than the first top surface, and a recess defined in the first portion. The second top surface is under the semiconductor wafer. The recess has a depth, and a distance between the pedestal and an inner surface of the recess is substantially equal to the depth of the recess.
    Type: Application
    Filed: July 12, 2022
    Publication date: November 3, 2022
    Inventors: HUNG-BIN LIN, LI-CHAO YIN, SHIH-TSUNG CHEN, YU-LUNG YANG, YING CHIEH WANG, BING KAI HUANG, SU-YU YEH
  • Publication number: 20220320104
    Abstract: A method for forming a memory includes: providing a substrate, a plurality of discrete bit line structures being located on the substrate, and an area surrounded by the adjacent bit line structures and the substrate and having a central axis; forming, on the substrate, a first conductive film filling an area between the adjacent bit line structures; etching the first conductive film by a first etching process to form a first conductive layer; forming a second conductive film on the top surface of the first conductive layer; and etching the second conductive film and the first conductive layer by a second etching process, the remaining second conductive film and the first conductive layer forming a capacitive contact window.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 6, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiao ZHU, YI-HSIANG CHEN, Lihui YANG, HUNG-I LIN, Yun-Chieh MI, Jinfeng GONG
  • Patent number: 11455046
    Abstract: An electronic device suitable for a stylus is provided. The electronic device includes a display panel, a touch module, and a processor. The display panel includes a display area. The touch module includes a touchable area. The processor is electrically connected to the display panel and the touch module. The processor defines an effective input area in the touchable area in response to the operation of the stylus, defines a mapping display area in the display area corresponding to the effective input area, and adjusts the display ratio of the mapping display area according to the input ratio of the effective input area.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 27, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Ya-Ting Chen, Hung-Yi Lin, Chien-Chih Tseng, Chun-Tsai Yeh, Wei-Tong Lin, Ming-Chieh Chen, Yi-Ou Wang, Chao-Chieh Cheng
  • Publication number: 20220299719
    Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11430692
    Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Lun Tsai, Huei-Wen Hsieh, Chun-Sheng Chen, Kai-Shiang Kuo, Jen-Wei Liu, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
  • Publication number: 20220255416
    Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.
    Type: Application
    Filed: January 6, 2022
    Publication date: August 11, 2022
    Inventors: Hung-Chieh LIN, Yi-Ping HSIEH, Jin-Zhong HUANG, Hung-Yu HUANG, Chih-Hsien LI, Ciao-Yin PAN
  • Patent number: 11411331
    Abstract: A power supply device includes a power supply housing having an accommodating space and an accommodating opening, a hybrid wire-to-wire connector structure and a circuit board disposed in the accommodating space. The hybrid wire-to-wire connector structure includes a connecting seat and an adapter seat. The connecting seat has a signal line terminal and a power line terminal. The connecting seat is disposed in the accommodating opening through an annular rib. The adapter seat has a signal conduction end and a power conduction end. The adapter seat has formed a hook corresponding to the annular rib. The connecting seat and the adapter seat are combined through the signal conduction end inserted in the signal line terminal, the power conduction end inserted in the power line terminal and the hook clamped with the annular rib. Therefore, the power and signal connectors are integrated so as to simplify the assembly.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: August 9, 2022
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Cheng-Chan Wu, Chao-Yi Huang, Hung-Chieh Lin
  • Publication number: 20220239230
    Abstract: An isolated conversion apparatus with magnetic bias balance control includes an isolated converter, a controller, and a magnetic bias balance circuit. The isolated converter includes a transformer, and a primary side of the transformer includes a primary-side winding and at least one switch bridge arm. The controller is coupled to the at least one switch bridge arm, and provides a pulse width modulation (PWM) signal group to control the at least one switch bridge arm. The magnetic bias balance circuit is coupled to two ends of the primary-side winding and the controller, and provides a compensation voltage to the controller according to an average voltage of a winding voltage across the two ends of the primary-side winding. The controller adjusts a duty cycle of the PWM signal group according to the compensation voltage to correct the magnetic bias.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 28, 2022
    Inventors: Chih-Hsien LI, Yi-Ping HSIEH, Hung-Chieh LIN, Hung-Yu HUANG, Ciao-Yin PAN
  • Patent number: 11387683
    Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Jer Wang, Ching-Nen Peng, Chewn-Pu Jou, Feng Wei Kuo, Hao Chen, Hung-Chih Lin, Huan-Neng Chen, Kuang-Kai Yen, Ming-Chieh Liu, Tsung-Hsiung Lee
  • Patent number: 11349336
    Abstract: A method for operating a power factor correction (PFC) circuit of an uninterruptible power supply (UPS) apparatus is provided. The PFC circuit includes two T-type converters, and each of the T-type converters includes four switching tubes. The method includes: converting AC input voltage into a positive bus voltage across a first capacitor and a negative bus voltage across a second capacitor that is connected in series with the first capacitor when the UPS apparatus is operated under a normal supply mode; and controlling conduction states of the switching tubes of the T-type converters to balance the positive bus voltage and the negative bus voltage when the UPS apparatus is operated under a battery supply mode.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 31, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yuan-Fang Lai, Hung-Chieh Lin, Chao-Li Kao, Chao-Lung Kuo, Hsin-Chih Chen, Yi-Ping Hsieh
  • Publication number: 20220045627
    Abstract: A conversion apparatus with a three-level switching circuit includes a DC conversion module, a three-level circuit, and a control unit. The three-level circuit includes a bridge arm assembly and a capacitor assembly. The capacitor assembly includes a first capacitor and a second capacitor connected to the first capacitor in series. The DC conversion module has a positive output end and a negative output end, and the positive output end and the negative output end are coupled to the bridge arm assembly. The control unit controls the switching of a second switch unit and a third switch unit to make the three-level circuit operate in a first state where the positive output end and the negative output end are connected to the first capacitor, and operate in a second state where the positive output end and the negative output end are connected to the second capacitor.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 10, 2022
    Inventors: Hung-Chieh LIN, Yi-Ping HSIEH, Jin-Zhong HUANG, Hung-Yu HUANG, Chih-Hsien LI
  • Patent number: D968391
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 1, 2022
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Chuan-Hao Wen, Liang-Jen Lin, Hung-Chieh Wu, Min-Chieh Yang, Chung-Wei Wu